litte bit of docs

This commit is contained in:
Torsten Ruger 2018-08-24 18:49:44 +03:00
parent 71ab369c71
commit f993ccefe3
3 changed files with 9 additions and 8 deletions

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@ -9,10 +9,11 @@ And a large part of that functionality must actually be used at compile time too
We reuse the Parfait code at compile-time, to create the data for the compiled code. We reuse the Parfait code at compile-time, to create the data for the compiled code.
To do this the compiler (re) defines the object memory (in parfait_adapter). To do this the compiler (re) defines the object memory (in parfait_adapter).
A work in progress that started from here : http://ruby-x.org/2014/06/10/more-clarity.html A work in progress that started from here : http://ruby-x.org/blog/more-clarity
went on here http://ruby-x.org/2014/07/05/layers-vs-passes.html went on here http://ruby-x.org/blog/layers-vs-passes.html
and is now documented here http://ruby-x.org/rubyx/parfait.html
A step back: the code (program) we compile runs at run - time. A step back: the code (program) we compile runs at run - time.
And so does parfait. So all we have to do is compile it with the program. And so does parfait. So all we have to do is compile it with the program.
And thus parfait can be used at run-time. And thus parfait can be used at run-time.

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@ -12,7 +12,7 @@ class Class
end end
end end
# The RiscMachine, is an abstract machine with registers. Think of it as an arm machine with # The Risc Machine, is an abstract machine with registers. Think of it as an arm machine with
# normal instruction names. It is not however an abstraction of existing hardware, but only # normal instruction names. It is not however an abstraction of existing hardware, but only
# of that subset that we need. # of that subset that we need.
# See risc/Readme # See risc/Readme

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@ -1,6 +1,6 @@
# Risc Machine # Risc Machine
The RiscMachine, is an abstract machine with registers. Think of it as an arm machine with The Risc Machine, is an abstract machine with registers. Think of it as an arm machine with
normal instruction names. It is not however an abstraction of existing hardware, but only normal instruction names. It is not however an abstraction of existing hardware, but only
of that subset that we need. of that subset that we need.
@ -9,7 +9,7 @@ Our primary objective is to compile typed code to this level, so the register ma
- object load - object load
- object oriented call semantics - object oriented call semantics
- extended (and extensible) branching - extended (and extensible) branching
- normal integer operators (but no sub word instructions) - normal integer operators
All data is in objects. All data is in objects.
@ -18,7 +18,7 @@ express call semantics.
## Calls and syscalls ## Calls and syscalls
The RiscMachine only uses 1 fixed register, the currently worked on Message. (and assumes a The Risc Machine only uses 1 fixed register, the currently worked on Message. (and assumes a
program counter and flags, neither of which are directly manipulated) program counter and flags, neither of which are directly manipulated)
There is no stack, rather messages form a linked list, and preparing to call, the data is There is no stack, rather messages form a linked list, and preparing to call, the data is
@ -30,7 +30,7 @@ the meaning or number of syscalls. This is implemented by the level below, eg th
## Interpreter ## Interpreter
There is an interpreter that can interpret compiled register machine programs. There is an interpreter that can interpret programs compiled to the risc instruction set.
This is very handy for debugging (and nothing else). This is very handy for debugging (and nothing else).
Even more handy is the graphical interface for the interpreter, which is in it's own repository: Even more handy is the graphical interface for the interpreter, which is in it's own repository: