cleaned up BIG time, instruction hierachy, better names, DRYd up a lot
This commit is contained in:
Torsten Ruger
parent
c98547137b
commit
f97205300f
@ -1,4 +1,7 @@
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require 'asm/instruction'
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require 'asm/call_instruction'
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require 'asm/stack_instruction'
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require 'asm/logic_instruction'
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require 'asm/memory_instruction'
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require 'asm/nodes'
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require 'asm/nodes'
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require 'stream_reader'
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require 'stream_reader'
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require 'stringio'
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require 'stringio'
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@ -6,118 +9,123 @@ require "asm/string_literal"
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module Asm
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module Asm
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class ArmAssembler
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class ArmAssembler
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%w(r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12
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r13 r14 r15 a1 a2 a3 a4 v1 v2 v3 v4 v5 v6
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rfp sl fp ip sp lr pc
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).each { |reg|
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define_method(reg) {
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Asm::Register.new(reg)
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}
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}
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def initialize
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@values = []
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@position = 0 # marks not set
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@labels = []
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@string_table = {}
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end
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attr_reader :values , :position
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def instruction(clazz,name, *args)
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opcode = name.to_s
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arg_nodes = []
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args.each { |arg|
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if (arg.is_a?(Asm::Register))
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arg_nodes << arg
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elsif (arg.is_a?(Integer))
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arg_nodes << Asm::NumLiteral.new(arg)
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elsif (arg.is_a?(String))
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arg_nodes << add_string(arg)
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elsif (arg.is_a?(Asm::Label))
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arg_nodes << arg
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else
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raise 'Invalid argument `%s\' for instruction' % arg.inspect
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end
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}
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add_value clazz.new(opcode , arg_nodes)
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end
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def self.define_instruction(inst , clazz )
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define_method(inst) do |*args|
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instruction clazz , inst.to_sym, *args
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end
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define_method(inst+'s') do |*args|
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instruction clazz , (inst+'s').to_sym, *args
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end
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%w(al eq ne cs mi hi cc pl ls vc lt le ge gt vs).each do |cond_suffix|
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define_method(inst+cond_suffix) do |*args|
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instruction clazz , (inst+cond_suffix).to_sym, *args
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end
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define_method(inst+'s'+cond_suffix) do |*args|
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instruction clazz , (inst+'s'+cond_suffix).to_sym, *args
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end
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end
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end
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["push", "pop"].each do |inst|
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define_instruction(inst , StackInstruction)
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end
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%w(adc add and bic eor orr rsb rsc sbc sub mov mvn cmn cmp teq tst b bl bx
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swi str strb ldr ldrb ).each do |inst|
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define_instruction(inst , Instruction)
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end
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def assemble_to_string
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#put the strings at the end of the assembled code.
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# adding them will fix their position and make them assemble after
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@string_table.values.each do |data|
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add_value data
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end
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io = StringIO.new
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assemble(io)
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io.string
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end
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def add_string str
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value = @string_table[str]
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return value if value
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data = Asm::StringLiteral.new(str)
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@string_table[str] = data
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end
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def strings
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@string_table.values
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end
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def add_value(val)
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val.at(@position)
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length = val.length
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@position += length
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@values << val
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end
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def label name
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label = Label.new(name , self)
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@labels << label
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label
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end
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def label! name
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label(name).set!
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end
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def assemble(io)
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@values.each do |obj|
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obj.assemble io, self
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end
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end
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InstructionTools::REGISTERS.each do |reg , number|
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define_method(reg) { Asm::Register.new(reg , number) }
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end
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end
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def initialize
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@values = []
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@position = 0 # marks not set
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@labels = []
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@string_table = {}
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end
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attr_reader :values , :position
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def instruction(clazz,name, *args)
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opcode = name.to_s
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arg_nodes = []
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args.each do |arg|
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if (arg.is_a?(Asm::Register))
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arg_nodes << arg
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elsif (arg.is_a?(Integer))
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arg_nodes << Asm::NumLiteral.new(arg)
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elsif (arg.is_a?(String))
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arg_nodes << add_string(arg)
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elsif (arg.is_a?(Asm::Label))
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arg_nodes << arg
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else
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raise "Invalid argument #{arg.inspect} for instruction"
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end
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end
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add_value clazz.new(opcode , arg_nodes)
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end
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def self.define_instruction(inst , clazz )
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define_method(inst) do |*args|
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instruction clazz , inst , *args
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end
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define_method(inst.to_s+'s') do |*args|
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instruction clazz , inst.to_s+'s' , *args
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end
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InstructionTools::COND_CODES.keys.each do |cond_suffix|
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suffix = cond_suffix.to_s
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define_method(inst.to_s + suffix) do |*args|
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instruction clazz , inst + suffix , *args
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end
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define_method(inst.to_s + 's'+ suffix) do |*args|
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instruction clazz , inst.to_s + 's' + suffix, *args
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end
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end
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end
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[:push, :pop].each do |inst|
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define_instruction(inst , StackInstruction)
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end
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[:adc, :add, :and, :bic, :eor, :orr, :rsb, :rsc, :sbc, :sub].each do |inst|
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define_instruction(inst , LogicInstruction)
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end
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[:mov, :mvn].each do |inst|
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define_instruction(inst , MoveInstruction)
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end
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[:cmn, :cmp, :teq, :tst].each do |inst|
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define_instruction(inst , CompareInstruction)
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end
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[:strb, :str , :ldrb, :ldr].each do |inst|
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define_instruction(inst , MemoryInstruction)
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end
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[:b, :bl , :swi].each do |inst|
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define_instruction(inst , CallInstruction)
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end
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def assemble_to_string
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#put the strings at the end of the assembled code.
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# adding them will fix their position and make them assemble after
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@string_table.values.each do |data|
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add_value data
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end
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io = StringIO.new
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assemble(io)
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io.string
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end
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def add_string str
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value = @string_table[str]
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return value if value
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data = Asm::StringLiteral.new(str)
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@string_table[str] = data
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end
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def strings
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@string_table.values
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end
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def add_value(val)
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val.at(@position)
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length = val.length
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@position += length
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@values << val
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end
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def label name
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label = Label.new(name , self)
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@labels << label
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label
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end
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def label! name
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label(name).set!
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end
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def assemble(io)
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@values.each do |obj|
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obj.assemble io, self
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end
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end
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end
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end
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end
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43
lib/asm/call_instruction.rb
Normal file
43
lib/asm/call_instruction.rb
Normal file
@ -0,0 +1,43 @@
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module Asm
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# ADDRESSING MODE 4 , Calling
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class CallInstruction < Instruction
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include Asm::InstructionTools
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def initialize(opcode , args)
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super(opcode,args)
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end
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def assemble(io, as)
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s = @update_status_flag? 1 : 0
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case opcode
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when :b, :bl
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arg = args[0]
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if arg.is_a? Label
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diff = arg.position - self.position - 8
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arg = NumLiteral.new(diff)
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end
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if (arg.is_a?(Asm::NumLiteral))
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jmp_val = arg.value >> 2
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packed = [jmp_val].pack('l')
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# signed 32-bit, condense to 24-bit
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# TODO add check that the value fits into 24 bits
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io << packed[0,3]
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else
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raise "else not coded #{arg.inspect}"
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end
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io.write_uint8 OPCODES[opcode] | (COND_CODES[@cond] << 4)
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when :swi
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arg = args[0]
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if (arg.is_a?(Asm::NumLiteral))
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packed = [arg.value].pack('L')[0,3]
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io << packed
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io.write_uint8 0b1111 | (COND_CODES[@cond] << 4)
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else
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raise Asm::AssemblyError.new("invalid operand argument expected literal not #{arg}")
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end
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end
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end
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end#class
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end
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@ -1,110 +1,47 @@
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require "asm/assembly_error"
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require "asm/assembly_error"
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require "asm/instruction_tools"
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require "asm/instruction_tools"
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require "asm/normal_builder"
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require "asm/memory_access_builder"
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require "asm/label"
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require "asm/label"
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module Asm
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module Asm
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class Instruction
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class Instruction
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include InstructionTools
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include InstructionTools
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COND_POSTFIXES = Regexp.union(%w(eq ne cs cc mi pl vs vc hi ls ge lt gt le al)).source
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COND_POSTFIXES = Regexp.union( COND_CODES.keys.collect{|k|k.to_s} ).source
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def initialize(opcode , args)
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opcode = opcode.downcase
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def initialize(opcode , args)
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@cond = 0b1011
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opcode = opcode.to_s.downcase
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if (opcode =~ /(#{COND_POSTFIXES})$/)
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@cond = :al
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@cond = $1.to_sym
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if (opcode =~ /(#{COND_POSTFIXES})$/)
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opcode = opcode[0..-3]
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@cond = $1.to_sym
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end unless opcode == 'teq'
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opcode = opcode[0..-3]
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if (opcode =~ /s$/)
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end unless opcode == 'teq'
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@s = true
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if (opcode =~ /s$/)
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opcode = opcode[0..-2]
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@update_status_flag= 1
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else
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opcode = opcode[0..-2]
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@s = false
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else
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end
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@update_status_flag= 0
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@opcode = opcode.downcase.to_sym
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@args = args
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end
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attr_reader :opcode, :args , :position
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def affect_status
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@s
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end
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def at position
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@position = position
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end
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def length
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4
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end
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def assemble(io, as)
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s = @s ? 1 : 0
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case opcode
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when :adc, :add, :and, :bic, :eor, :orr, :rsb, :rsc, :sbc, :sub
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builder = NormalBuilder.new(OPC_DATA_PROCESSING, OPCODES[opcode], s)
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builder.cond = COND_CODES[@cond]
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builder.rd = reg_ref(args[0])
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builder.rn = reg_ref(args[1])
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builder.build_operand args[2] , self.position
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builder.assemble io, as
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when :cmn, :cmp, :teq, :tst
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builder = NormalBuilder.new(OPC_DATA_PROCESSING, OPCODES[opcode], 1)
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builder.cond = COND_CODES[@cond]
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builder.rn = reg_ref(args[0])
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builder.rd = 0
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builder.build_operand args[1]
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builder.assemble io, as
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when :mov, :mvn
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builder = NormalBuilder.new(OPC_DATA_PROCESSING, OPCODES[opcode], s)
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builder.cond = COND_CODES[@cond]
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builder.rn = 0
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builder.rd = reg_ref(args[0])
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builder.build_operand args[1]
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builder.assemble io, as
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when :strb, :str
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builder = MemoryAccessBuilder.new(OPC_MEMORY_ACCESS, (opcode == :strb ? 1 : 0), 0)
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builder.cond = COND_CODES[@cond]
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builder.rd = reg_ref(args[1])
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builder.build_operand args[0]
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builder.assemble io, as, self
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when :ldrb, :ldr
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builder = MemoryAccessBuilder.new(OPC_MEMORY_ACCESS, (opcode == :ldrb ? 1 : 0), 1)
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builder.cond = COND_CODES[@cond]
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builder.rd = reg_ref(args[0])
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builder.build_operand args[1]
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builder.assemble io, as, self
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when :b, :bl
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arg = args[0]
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if arg.is_a? Label
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diff = arg.position - self.position - 8
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arg = NumLiteral.new(diff)
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end
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if (arg.is_a?(Asm::NumLiteral))
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jmp_val = arg.value >> 2
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packed = [jmp_val].pack('l')
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# signed 32-bit, condense to 24-bit
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# TODO add check that the value fits into 24 bits
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io << packed[0,3]
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else
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raise "else not coded #{arg.inspect}"
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end
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io.write_uint8 OPCODES[opcode] | (COND_CODES[@cond] << 4)
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when :swi
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arg = args[0]
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if (arg.is_a?(Asm::NumLiteral))
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packed = [arg.value].pack('L')[0,3]
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io << packed
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io.write_uint8 0b1111 | (COND_CODES[@cond] << 4)
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else
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raise Asm::AssemblyError.new("invalid operand argument expected literal not #{arg}")
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end
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else
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|
||||||
raise Asm::AssemblyError.new("unknown instruction #{opcode} #{self}")
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
|
@opcode = opcode.downcase.to_sym
|
||||||
|
@args = args
|
||||||
|
@operand = 0
|
||||||
end
|
end
|
||||||
|
attr_reader :opcode, :args , :position , :cond , :operand , :update_status_flag
|
||||||
|
|
||||||
|
def affect_status
|
||||||
|
@s
|
||||||
|
end
|
||||||
|
|
||||||
|
def at position
|
||||||
|
@position = position
|
||||||
|
end
|
||||||
|
|
||||||
|
def length
|
||||||
|
4
|
||||||
|
end
|
||||||
|
|
||||||
|
def assemble(io, as)
|
||||||
|
raise "Abstract class, should not be called/instantiated #{self.inspect}"
|
||||||
|
end
|
||||||
|
end
|
||||||
end
|
end
|
||||||
@ -1,81 +1,86 @@
|
|||||||
module Asm
|
module Asm
|
||||||
|
|
||||||
module InstructionTools
|
module InstructionTools
|
||||||
OPCODES = {
|
OPCODES = {
|
||||||
:adc => 0b0101, :add => 0b0100,
|
:adc => 0b0101, :add => 0b0100,
|
||||||
:and => 0b0000, :bic => 0b1110,
|
:and => 0b0000, :bic => 0b1110,
|
||||||
:eor => 0b0001, :orr => 0b1100,
|
:eor => 0b0001, :orr => 0b1100,
|
||||||
:rsb => 0b0011, :rsc => 0b0111,
|
:rsb => 0b0011, :rsc => 0b0111,
|
||||||
:sbc => 0b0110, :sub => 0b0010,
|
:sbc => 0b0110, :sub => 0b0010,
|
||||||
|
|
||||||
# for these Rn is sbz (should be zero)
|
# for these Rn is sbz (should be zero)
|
||||||
:mov => 0b1101,
|
:mov => 0b1101,
|
||||||
:mvn => 0b1111,
|
:mvn => 0b1111,
|
||||||
# for these Rd is sbz and S=1
|
# for these Rd is sbz and S=1
|
||||||
:cmn => 0b1011,
|
:cmn => 0b1011,
|
||||||
:cmp => 0b1010,
|
:cmp => 0b1010,
|
||||||
:teq => 0b1001,
|
:teq => 0b1001,
|
||||||
:tst => 0b1000,
|
:tst => 0b1000,
|
||||||
|
|
||||||
:b => 0b1010,
|
:b => 0b1010,
|
||||||
:bl => 0b1011,
|
:bl => 0b1011,
|
||||||
:bx => 0b00010010
|
:bx => 0b00010010
|
||||||
}
|
}
|
||||||
COND_CODES = {
|
#return the bit patter that the cpu uses for the current instruction @opcode
|
||||||
:al => 0b1110, :eq => 0b0000,
|
def op_bit_code
|
||||||
:ne => 0b0001, :cs => 0b0010,
|
OPCODES[@opcode] or throw "no code found for #{@opcode.inspect}"
|
||||||
:mi => 0b0100, :hi => 0b1000,
|
|
||||||
:cc => 0b0011, :pl => 0b0101,
|
|
||||||
:ls => 0b1001, :vc => 0b0111,
|
|
||||||
:lt => 0b1011, :le => 0b1101,
|
|
||||||
:ge => 0b1010, :gt => 0b1100,
|
|
||||||
:vs => 0b0110
|
|
||||||
}
|
|
||||||
OPC_DATA_PROCESSING = 0b00
|
|
||||||
OPC_MEMORY_ACCESS = 0b01
|
|
||||||
OPC_STACK = 0b10
|
|
||||||
|
|
||||||
def reg_ref(arg)
|
|
||||||
if (not arg.is_a?(Asm::Register))
|
|
||||||
raise Asm::AssemblyError.new("argument must be a register not #{arg}")
|
|
||||||
end
|
|
||||||
|
|
||||||
ref =
|
|
||||||
{'r0' => 0, 'r1' => 1, 'r2' => 2, 'r3' => 3, 'r4' => 4, 'r5' => 5,
|
|
||||||
'r6' => 6, 'r7' => 7, 'r8' => 8, 'r9' => 9, 'r10' => 10, 'r11' => 11,
|
|
||||||
'r12' => 12, 'r13' => 13, 'r14' => 14, 'r15' => 15, 'a1' => 0, 'a2' => 1,
|
|
||||||
'a3' => 2, 'a4' => 3, 'v1' => 4, 'v2' => 5, 'v3' => 6, 'v4' => 7, 'v5' => 8,
|
|
||||||
'v6' => 9, 'rfp' => 9, 'sl' => 10, 'fp' => 11, 'ip' => 12, 'sp' => 13,
|
|
||||||
'lr' => 14, 'pc' => 15}[arg.name.downcase]
|
|
||||||
|
|
||||||
if (not ref)
|
|
||||||
raise Asm::AssemblyError.new("unknown register #{arg}")
|
|
||||||
end
|
|
||||||
|
|
||||||
ref
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
|
|
||||||
def calculate_u8_with_rr(arg)
|
#codition codes can be applied to many instructions and thus save branches
|
||||||
parts = arg.value.to_s(2).rjust(32,'0').scan(/^(0*)(.+?)0*$/).flatten
|
# :al => always , :eq => equal and so on
|
||||||
pre_zeros = parts[0].length
|
# eq mov if equal :moveq r1 r2 (also exists as function) will only execute if the last operation was 0
|
||||||
imm_len = parts[1].length
|
COND_CODES = {
|
||||||
if ((pre_zeros+imm_len) % 2 == 1)
|
:al => 0b1110, :eq => 0b0000,
|
||||||
u8_imm = (parts[1]+'0').to_i(2)
|
:ne => 0b0001, :cs => 0b0010,
|
||||||
imm_len += 1
|
:mi => 0b0100, :hi => 0b1000,
|
||||||
else
|
:cc => 0b0011, :pl => 0b0101,
|
||||||
u8_imm = parts[1].to_i(2)
|
:ls => 0b1001, :vc => 0b0111,
|
||||||
end
|
:lt => 0b1011, :le => 0b1101,
|
||||||
if (u8_imm.fits_u8?)
|
:ge => 0b1010, :gt => 0b1100,
|
||||||
# can do!
|
:vs => 0b0110
|
||||||
rot_imm = (pre_zeros+imm_len) / 2
|
}
|
||||||
if (rot_imm > 15)
|
#return the bit pattern for the @cond variable, which signals the conditional code
|
||||||
return nil
|
def cond_bit_code
|
||||||
end
|
COND_CODES[@cond] or throw "no code found for #{@cond}"
|
||||||
return u8_imm | (rot_imm << 8)
|
|
||||||
else
|
|
||||||
return nil
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
|
|
||||||
|
OPC_DATA_PROCESSING = 0b00
|
||||||
|
OPC_MEMORY_ACCESS = 0b01
|
||||||
|
OPC_STACK = 0b10
|
||||||
|
|
||||||
|
REGISTERS = { 'r0' => 0, 'r1' => 1, 'r2' => 2, 'r3' => 3, 'r4' => 4, 'r5' => 5,
|
||||||
|
'r6' => 6, 'r7' => 7, 'r8' => 8, 'r9' => 9, 'r10' => 10, 'r11' => 11,
|
||||||
|
'r12' => 12, 'r13' => 13, 'r14' => 14, 'r15' => 15, 'a1' => 0, 'a2' => 1,
|
||||||
|
'a3' => 2, 'a4' => 3, 'v1' => 4, 'v2' => 5, 'v3' => 6, 'v4' => 7, 'v5' => 8,
|
||||||
|
'v6' => 9, 'rfp' => 9, 'sl' => 10, 'fp' => 11, 'ip' => 12, 'sp' => 13,
|
||||||
|
'lr' => 14, 'pc' => 15 }
|
||||||
|
def reg name
|
||||||
|
raise "no such register #{reg}" unless REGISTERS[name]
|
||||||
|
Asm::Register.new(name , REGISTERS[name])
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
def calculate_u8_with_rr(arg)
|
||||||
|
parts = arg.value.to_s(2).rjust(32,'0').scan(/^(0*)(.+?)0*$/).flatten
|
||||||
|
pre_zeros = parts[0].length
|
||||||
|
imm_len = parts[1].length
|
||||||
|
if ((pre_zeros+imm_len) % 2 == 1)
|
||||||
|
u8_imm = (parts[1]+'0').to_i(2)
|
||||||
|
imm_len += 1
|
||||||
|
else
|
||||||
|
u8_imm = parts[1].to_i(2)
|
||||||
|
end
|
||||||
|
if (u8_imm.fits_u8?)
|
||||||
|
# can do!
|
||||||
|
rot_imm = (pre_zeros+imm_len) / 2
|
||||||
|
if (rot_imm > 15)
|
||||||
|
return nil
|
||||||
|
end
|
||||||
|
return u8_imm | (rot_imm << 8)
|
||||||
|
else
|
||||||
|
return nil
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
end
|
end
|
||||||
105
lib/asm/logic_instruction.rb
Normal file
105
lib/asm/logic_instruction.rb
Normal file
@ -0,0 +1,105 @@
|
|||||||
|
module Asm
|
||||||
|
# ADDRESSING MODE 1
|
||||||
|
# Logic ,Maths, Move and compare instructions (last three below)
|
||||||
|
|
||||||
|
class LogicInstruction < Instruction
|
||||||
|
include Asm::InstructionTools
|
||||||
|
|
||||||
|
def initialize( opcode , args)
|
||||||
|
super(opcode , args)
|
||||||
|
@inst_class = OPC_DATA_PROCESSING
|
||||||
|
@i = 0
|
||||||
|
@rd = args[0]
|
||||||
|
end
|
||||||
|
attr_accessor :inst_class, :i, :rn, :rd
|
||||||
|
|
||||||
|
# Build representation for source value
|
||||||
|
def build
|
||||||
|
@rn = args[1]
|
||||||
|
do_build args[2]
|
||||||
|
end
|
||||||
|
|
||||||
|
#(stays in subclases, while build is overriden to provide different arguments)
|
||||||
|
def do_build(arg)
|
||||||
|
if arg.is_a?(Asm::StringLiteral)
|
||||||
|
# do pc relative addressing with the difference to the instuction
|
||||||
|
# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
|
||||||
|
arg = Asm::NumLiteral.new( arg.position - self.position - 8 )
|
||||||
|
end
|
||||||
|
if (arg.is_a?(Asm::NumLiteral))
|
||||||
|
if (arg.value.fits_u8?)
|
||||||
|
# no shifting needed
|
||||||
|
@operand = arg.value
|
||||||
|
@i = 1
|
||||||
|
elsif (op_with_rot = calculate_u8_with_rr(arg))
|
||||||
|
@operand = op_with_rot
|
||||||
|
@i = 1
|
||||||
|
else
|
||||||
|
raise Asm::AssemblyError.new("cannot fit numeric literal argument in operand #{arg}")
|
||||||
|
end
|
||||||
|
elsif (arg.is_a?(Asm::Register))
|
||||||
|
@operand = arg
|
||||||
|
@i = 0
|
||||||
|
elsif (arg.is_a?(Asm::Shift))
|
||||||
|
rm_ref = arg.argument
|
||||||
|
@i = 0
|
||||||
|
shift_op = {'lsl' => 0b000, 'lsr' => 0b010, 'asr' => 0b100,
|
||||||
|
'ror' => 0b110, 'rrx' => 0b110}[arg.type]
|
||||||
|
if (arg.type == 'ror' and arg.value.nil?)
|
||||||
|
# ror #0 == rrx
|
||||||
|
raise Asm::AssemblyError.new('cannot rotate by zero', arg)
|
||||||
|
end
|
||||||
|
|
||||||
|
arg1 = arg.value
|
||||||
|
if (arg1.is_a?(Asm::NumLiteral))
|
||||||
|
if (arg1.value >= 32)
|
||||||
|
raise Asm::AssemblyError.new('cannot shift by more than 31', arg1)
|
||||||
|
end
|
||||||
|
shift_imm = arg1.value
|
||||||
|
elsif (arg1.is_a?(Asm::Register))
|
||||||
|
shift_op val |= 0x1;
|
||||||
|
shift_imm = arg1.number << 1
|
||||||
|
elsif (arg.type == 'rrx')
|
||||||
|
shift_imm = 0
|
||||||
|
end
|
||||||
|
|
||||||
|
@operand = rm_ref | (shift_op << 4) | (shift_imm << 4+3)
|
||||||
|
else
|
||||||
|
raise Asm::AssemblyError.new("invalid operand argument #{arg.inspect}")
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
def assemble(io, as)
|
||||||
|
build
|
||||||
|
val = operand.is_a?(Register) ? operand.bits : operand
|
||||||
|
val |= (rd.bits << 12)
|
||||||
|
val |= (rn.bits << 12+4)
|
||||||
|
val |= (update_status_flag << 12+4+4)#20
|
||||||
|
val |= (op_bit_code << 12+4+4 +1)
|
||||||
|
val |= (i << 12+4+4 +1+4)
|
||||||
|
val |= (inst_class << 12+4+4 +1+4+1)
|
||||||
|
val |= (cond_bit_code << 12+4+4 +1+4+1+2)
|
||||||
|
io.write_uint32 val
|
||||||
|
end
|
||||||
|
end
|
||||||
|
class CompareInstruction < LogicInstruction
|
||||||
|
def initialize( opcode , args)
|
||||||
|
super(opcode , args)
|
||||||
|
@update_status_flag = 1
|
||||||
|
@rn = args[0]
|
||||||
|
@rd = reg "r0"
|
||||||
|
end
|
||||||
|
def build
|
||||||
|
do_build args[1]
|
||||||
|
end
|
||||||
|
end
|
||||||
|
class MoveInstruction < LogicInstruction
|
||||||
|
def initialize( opcode , args)
|
||||||
|
super(opcode , args)
|
||||||
|
@rn = reg "r0" # register zero = zero bit pattern
|
||||||
|
end
|
||||||
|
def build
|
||||||
|
do_build args[1]
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
@ -1,74 +0,0 @@
|
|||||||
require "asm/nodes"
|
|
||||||
|
|
||||||
module Asm
|
|
||||||
# ADDRESSING MODE 2
|
|
||||||
# Implemented: immediate offset with offset=0
|
|
||||||
class MemoryAccessBuilder
|
|
||||||
include Asm::InstructionTools
|
|
||||||
|
|
||||||
def initialize(inst_class, byte_access, load_store)
|
|
||||||
@cond = 0b1110
|
|
||||||
@inst_class = 0
|
|
||||||
@i = 0 #I flag (third bit)
|
|
||||||
@pre_post_index = 0 #P flag
|
|
||||||
@add_offset = 0 #U flag
|
|
||||||
@byte_access = 0 #B flag
|
|
||||||
@w = 0 #W flag
|
|
||||||
@load_store = 0 #L flag
|
|
||||||
@rn = 0
|
|
||||||
@rd = 0
|
|
||||||
@operand = 0
|
|
||||||
@inst_class = inst_class
|
|
||||||
@byte_access = byte_access
|
|
||||||
@load_store = load_store
|
|
||||||
end
|
|
||||||
attr_accessor :cond, :inst_class, :i, :pre_post_index, :add_offset,
|
|
||||||
:byte_access, :w, :load_store, :rn, :rd, :operand
|
|
||||||
|
|
||||||
# Build representation for target address
|
|
||||||
def build_operand(arg)
|
|
||||||
#str / ldr are _serious instructions. With BIG possibilities not half are implemented
|
|
||||||
@i = 0
|
|
||||||
@pre_post_index = 0
|
|
||||||
@w = 0
|
|
||||||
@operand = 0
|
|
||||||
if (arg.is_a?(Asm::Register))
|
|
||||||
@rn = reg_ref(arg)
|
|
||||||
if(arg.offset != 0)
|
|
||||||
@operand = arg.offset
|
|
||||||
if (@operand < 0)
|
|
||||||
@add_offset = 0
|
|
||||||
#TODO test/check/understand
|
|
||||||
@operand *= -1
|
|
||||||
else
|
|
||||||
@add_offset = 1
|
|
||||||
end
|
|
||||||
if (@operand.abs > 4095)
|
|
||||||
raise Asm::AssemblyError.new("reference offset too large/small (max 4095) #{argr.right}" )
|
|
||||||
end
|
|
||||||
end
|
|
||||||
elsif (arg.is_a?(Asm::Label) or arg.is_a?(Asm::NumLiteral))
|
|
||||||
@pre_post_index = 1
|
|
||||||
@rn = 15 # pc
|
|
||||||
@use_addrtable_reloc = true
|
|
||||||
@addrtable_reloc_target = arg
|
|
||||||
else
|
|
||||||
raise Asm::AssemblyError.new("invalid operand argument #{arg.inspect}")
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
def assemble(io, as, inst)
|
|
||||||
#not sure about these 2 constants. They produce the correct output for str r0 , r1
|
|
||||||
# but i can't help thinking that that is because they are not used in that instruction and
|
|
||||||
# so it doesn't matter. Will see
|
|
||||||
@add_offset = 1
|
|
||||||
@pre_post_index = 1
|
|
||||||
val = operand | (rd << 12 ) | (rn << 12 + 4) |
|
|
||||||
(load_store << 12+4+4) | (w << 12+4+4+1) |
|
|
||||||
(byte_access << 12+4+4+1+1) | (add_offset << 12+4+4+1+1+1) |
|
|
||||||
(pre_post_index << 12+4+4+1+1+1+1) | (i << 12+4+4+1+1+1+1+1) |
|
|
||||||
(inst_class << 12+4+4+1+1+1+1+1+1) | (cond << 12+4+4+1+1+1+1+1+1+2)
|
|
||||||
io.write_uint32 val
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
80
lib/asm/memory_instruction.rb
Normal file
80
lib/asm/memory_instruction.rb
Normal file
@ -0,0 +1,80 @@
|
|||||||
|
require "asm/nodes"
|
||||||
|
|
||||||
|
module Asm
|
||||||
|
# ADDRESSING MODE 2
|
||||||
|
# Implemented: immediate offset with offset=0
|
||||||
|
class MemoryInstruction < Instruction
|
||||||
|
include Asm::InstructionTools
|
||||||
|
|
||||||
|
def initialize(opcode , args)
|
||||||
|
super( opcode , args )
|
||||||
|
@inst_class = OPC_MEMORY_ACCESS
|
||||||
|
@i = 0 #I flag (third bit)
|
||||||
|
@pre_post_index = 0 #P flag
|
||||||
|
@add_offset = 0 #U flag
|
||||||
|
@byte_access = opcode.to_s[-1] == "b" ? 1 : 0 #B (byte) flag
|
||||||
|
@w = 0 #W flag
|
||||||
|
@is_load = opcode.to_s[0] == "l" ? 1 : 0 #L (load) flag
|
||||||
|
@rn = reg "r0" # register zero = zero bit pattern
|
||||||
|
@rd = reg "r0" # register zero = zero bit pattern
|
||||||
|
end
|
||||||
|
attr_accessor :inst_class, :i, :pre_post_index, :add_offset,
|
||||||
|
:byte_access, :w, :is_load, :rn, :rd
|
||||||
|
|
||||||
|
# Build representation for target address
|
||||||
|
def build
|
||||||
|
if( @is_load )
|
||||||
|
@rd = args[0]
|
||||||
|
arg = args[1]
|
||||||
|
else #store
|
||||||
|
@rd = args[1]
|
||||||
|
arg = args[0]
|
||||||
|
end
|
||||||
|
#str / ldr are _serious instructions. With BIG possibilities not half are implemented
|
||||||
|
if (arg.is_a?(Asm::Register))
|
||||||
|
@rn = arg
|
||||||
|
if(arg.offset != 0)
|
||||||
|
@operand = arg.offset
|
||||||
|
if (@operand < 0)
|
||||||
|
@add_offset = 0
|
||||||
|
#TODO test/check/understand
|
||||||
|
@operand *= -1
|
||||||
|
else
|
||||||
|
@add_offset = 1
|
||||||
|
end
|
||||||
|
if (@operand.abs > 4095)
|
||||||
|
raise Asm::AssemblyError.new("reference offset too large/small (max 4095) #{argr.right}" )
|
||||||
|
end
|
||||||
|
end
|
||||||
|
elsif (arg.is_a?(Asm::Label) or arg.is_a?(Asm::NumLiteral))
|
||||||
|
@pre_post_index = 1
|
||||||
|
@rn = pc
|
||||||
|
@use_addrtable_reloc = true
|
||||||
|
@addrtable_reloc_target = arg
|
||||||
|
else
|
||||||
|
raise Asm::AssemblyError.new("invalid operand argument #{arg.inspect}")
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
def assemble(io, as)
|
||||||
|
build
|
||||||
|
#not sure about these 2 constants. They produce the correct output for str r0 , r1
|
||||||
|
# but i can't help thinking that that is because they are not used in that instruction and
|
||||||
|
# so it doesn't matter. Will see
|
||||||
|
@add_offset = 1
|
||||||
|
@pre_post_index = 1
|
||||||
|
val = operand
|
||||||
|
val |= (rd.bits << 12 )
|
||||||
|
val |= (rn.bits << 12+4) #16
|
||||||
|
val |= (is_load << 12+4 +4)
|
||||||
|
val |= (w << 12+4 +4+1)
|
||||||
|
val |= (byte_access << 12+4 +4+1+1)
|
||||||
|
val |= (add_offset << 12+4 +4+1+1+1)
|
||||||
|
val |= (pre_post_index << 12+4 +4+1+1+1+1)#24
|
||||||
|
val |= (i << 12+4 +4+1+1+1+1 +1)
|
||||||
|
val |= (inst_class << 12+4 +4+1+1+1+1 +1+1)
|
||||||
|
val |= (cond_bit_code << 12+4 +4+1+1+1+1 +1+1+2)
|
||||||
|
io.write_uint32 val
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
@ -9,9 +9,10 @@ module Asm
|
|||||||
# Arm has addressing modes abound, and so can add to a register before actually using it
|
# Arm has addressing modes abound, and so can add to a register before actually using it
|
||||||
# If can actually shift or indeed shift what it adds, but not implemented
|
# If can actually shift or indeed shift what it adds, but not implemented
|
||||||
class Register
|
class Register
|
||||||
attr_accessor :name , :offset
|
attr_accessor :name , :offset , :bits
|
||||||
def initialize name
|
def initialize name , bits
|
||||||
@name = name
|
@name = name
|
||||||
|
@bits = bits
|
||||||
@offset = 0
|
@offset = 0
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|||||||
@ -1,82 +0,0 @@
|
|||||||
module Asm
|
|
||||||
# ADDRESSING MODE 1
|
|
||||||
# Complete!
|
|
||||||
class NormalBuilder
|
|
||||||
include Asm::InstructionTools
|
|
||||||
|
|
||||||
def initialize(inst_class, opcode, s)
|
|
||||||
@cond = 0b1110
|
|
||||||
@inst_class = 0
|
|
||||||
@i = 0
|
|
||||||
@s = 0
|
|
||||||
@rn = 0
|
|
||||||
@rd = 0
|
|
||||||
@operand = 0
|
|
||||||
@inst_class = inst_class
|
|
||||||
@opcode = opcode
|
|
||||||
@s = s
|
|
||||||
end
|
|
||||||
attr_accessor :cond, :inst_class, :i, :opcode, :s,
|
|
||||||
:rn, :rd, :operand
|
|
||||||
|
|
||||||
# Build representation for source value
|
|
||||||
def build_operand(arg , position = 0)
|
|
||||||
#position only needed for calculating relative addresses to data objects
|
|
||||||
#there is a design stink here which makes my head ache. But shanti shanti
|
|
||||||
if arg.is_a?(Asm::StringLiteral)
|
|
||||||
# do pc relative addressing with the difference to the instuction
|
|
||||||
# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
|
|
||||||
arg = Asm::NumLiteral.new( arg.position - position - 8 )
|
|
||||||
end
|
|
||||||
if (arg.is_a?(Asm::NumLiteral))
|
|
||||||
if (arg.value.fits_u8?)
|
|
||||||
# no shifting needed
|
|
||||||
@operand = arg.value
|
|
||||||
@i = 1
|
|
||||||
elsif (op_with_rot = calculate_u8_with_rr(arg))
|
|
||||||
@operand = op_with_rot
|
|
||||||
@i = 1
|
|
||||||
else
|
|
||||||
raise Asm::AssemblyError.new("cannot fit numeric literal argument in operand #{arg}")
|
|
||||||
end
|
|
||||||
elsif (arg.is_a?(Asm::Register))
|
|
||||||
@operand = reg_ref(arg)
|
|
||||||
@i = 0
|
|
||||||
elsif (arg.is_a?(Asm::Shift))
|
|
||||||
rm_ref = reg_ref(arg.argument)
|
|
||||||
@i = 0
|
|
||||||
shift_op = {'lsl' => 0b000, 'lsr' => 0b010, 'asr' => 0b100,
|
|
||||||
'ror' => 0b110, 'rrx' => 0b110}[arg.type]
|
|
||||||
if (arg.type == 'ror' and arg.value.nil?)
|
|
||||||
# ror #0 == rrx
|
|
||||||
raise Asm::AssemblyError.new('cannot rotate by zero', arg)
|
|
||||||
end
|
|
||||||
|
|
||||||
arg1 = arg.value
|
|
||||||
if (arg1.is_a?(Asm::NumLiteral))
|
|
||||||
if (arg1.value >= 32)
|
|
||||||
raise Asm::AssemblyError.new('cannot shift by more than 31', arg1)
|
|
||||||
end
|
|
||||||
shift_imm = arg1.value
|
|
||||||
elsif (arg1.is_a?(Asm::Register))
|
|
||||||
shift_op |= 0x1;
|
|
||||||
shift_imm = reg_ref(arg1) << 1
|
|
||||||
elsif (arg.type == 'rrx')
|
|
||||||
shift_imm = 0
|
|
||||||
end
|
|
||||||
|
|
||||||
@operand = rm_ref | (shift_op << 4) | (shift_imm << 4+3)
|
|
||||||
else
|
|
||||||
raise Asm::AssemblyError.new("invalid operand argument #{arg.inspect}")
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
def assemble(io, as)
|
|
||||||
val = operand | (rd << 12) | (rn << 12+4) |
|
|
||||||
(s << 12+4+4) | (opcode << 12+4+4+1) |
|
|
||||||
(i << 12+4+4+1+4) | (inst_class << 12+4+4+1+4+1) |
|
|
||||||
(cond << 12+4+4+1+4+1+2)
|
|
||||||
io.write_uint32 val
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
@ -1,65 +1,59 @@
|
|||||||
require "asm/instruction"
|
require "asm/instruction"
|
||||||
|
|
||||||
module Asm
|
module Asm
|
||||||
# ADDRESSING MODE 4
|
# ADDRESSING MODE 4
|
||||||
class StackInstruction < Instruction
|
class StackInstruction < Instruction
|
||||||
include Asm::InstructionTools
|
include Asm::InstructionTools
|
||||||
|
|
||||||
def initialize(opcode , args)
|
def initialize(opcode , args)
|
||||||
super(opcode,args)
|
super(opcode,args)
|
||||||
@operand = 0
|
@inst_class = Asm::Instruction::OPC_STACK
|
||||||
@cond = 0b1110
|
@update_status_flag= 0
|
||||||
@inst_class = Asm::Instruction::OPC_STACK
|
@rn = reg "r0" # register zero = zero bit pattern
|
||||||
@s = 0
|
# downward growing, decrement before memory access
|
||||||
@rn = 0
|
# official ARM style stack as used by gas
|
||||||
# downward growing, decrement before memory access
|
@write_base = 1
|
||||||
# official ARM style stack as used by gas
|
if (opcode == :push)
|
||||||
@write_base = 1
|
@pre_post_index = 1
|
||||||
if (opcode == :push)
|
@up_down = 0
|
||||||
@pre_post_index = 1
|
@is_pop = 0
|
||||||
@up_down = 0
|
else #pop
|
||||||
@store_load = 0
|
@pre_post_index = 0
|
||||||
else #pop
|
@up_down = 1
|
||||||
@pre_post_index = 0
|
@is_pop = 1
|
||||||
@up_down = 1
|
|
||||||
@store_load = 1
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
attr_accessor :cond, :inst_class, :pre_post_index, :up_down,
|
|
||||||
:s, :write_base, :store_load, :rn, :operand
|
|
||||||
|
|
||||||
def assemble(io, as)
|
|
||||||
cond = @cond.is_a?(Symbol) ? COND_CODES[@cond] : @cond
|
|
||||||
rn = 13 # sp
|
|
||||||
build_operand args
|
|
||||||
|
|
||||||
#assemble of old
|
|
||||||
val = @operand
|
|
||||||
val |= (rn << 16)
|
|
||||||
val |= (store_load << 16+4) #20
|
|
||||||
val |= (write_base << 16+4+ 1)
|
|
||||||
val |= (s << 16+4+ 1+1)
|
|
||||||
val |= (up_down << 16+4+ 1+1+1)
|
|
||||||
val |= (pre_post_index << 16+4+ 1+1+1+1)#24
|
|
||||||
val |= (inst_class << 16+4+ 1+1+1+1 +2)
|
|
||||||
val |= (cond << 16+4+ 1+1+1+1 +2+2)
|
|
||||||
puts "#{self.inspect}"
|
|
||||||
io.write_uint32 val
|
|
||||||
end
|
|
||||||
|
|
||||||
private
|
|
||||||
# Build representation for source value
|
|
||||||
def build_operand(arg)
|
|
||||||
if (arg.is_a?(Array))
|
|
||||||
@operand = 0
|
|
||||||
arg.each do |reg |
|
|
||||||
reg = reg_ref(reg)
|
|
||||||
@operand |= (1 << reg)
|
|
||||||
end
|
|
||||||
else
|
|
||||||
raise Asm::AssemblyError.new("invalid operand argument #{arg.inspect}")
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
end
|
end
|
||||||
|
attr_accessor :cond, :inst_class, :pre_post_index, :up_down,
|
||||||
|
:update_status_flag, :write_base, :is_pop, :rn, :operand
|
||||||
|
|
||||||
|
def assemble(io, as)
|
||||||
|
build
|
||||||
|
cond = @cond.is_a?(Symbol) ? COND_CODES[@cond] : @cond
|
||||||
|
rn = reg "sp" # sp register
|
||||||
|
#assemble of old
|
||||||
|
val = operand
|
||||||
|
val |= (rn.bits << 16)
|
||||||
|
val |= (is_pop << 16+4) #20
|
||||||
|
val |= (write_base << 16+4+ 1)
|
||||||
|
val |= (update_status_flag << 16+4+ 1+1)
|
||||||
|
val |= (up_down << 16+4+ 1+1+1)
|
||||||
|
val |= (pre_post_index << 16+4+ 1+1+1+1)#24
|
||||||
|
val |= (inst_class << 16+4+ 1+1+1+1 +2)
|
||||||
|
val |= (cond << 16+4+ 1+1+1+1 +2+2)
|
||||||
|
io.write_uint32 val
|
||||||
|
end
|
||||||
|
|
||||||
|
private
|
||||||
|
# Build representation for source value
|
||||||
|
def build
|
||||||
|
if (args.is_a?(Array))
|
||||||
|
@operand = 0
|
||||||
|
args.each do |reg |
|
||||||
|
@operand |= (1 << reg.bits)
|
||||||
|
end
|
||||||
|
else
|
||||||
|
raise Asm::AssemblyError.new("invalid operand argument #{args.inspect}")
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
end
|
end
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user