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removed arm and use as gem

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This commit is contained in:
Torsten Ruger 2015-07-18 14:12:20 +03:00
parent bae476657a
commit f4f703975b
32 changed files with 10 additions and 1452 deletions
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2
Gemfile
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@ -6,6 +6,8 @@ gem "rake"
gem "salama-reader" , :github => "salama/salama-reader"
gem "salama-object-file" , :github => "salama/salama-object-file"
gem "salama-arm" , :github => "salama/salama-arm"
gem "codeclimate-test-reporter", require: nil
group :development do

7
Gemfile.lock
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@ -1,3 +1,9 @@
GIT
remote: git://github.com/salama/salama-arm.git
revision: 9a1c18dfe974909e02e33f7b086ac516e3384f4b
specs:
salama-arm (0.0.1)
GIT
remote: git://github.com/salama/salama-object-file.git
revision: 9e49f2e725dbad48edc151419882b159505b2e9b
@ -47,5 +53,6 @@ DEPENDENCIES
rake
rubygems-tasks
salama!
salama-arm!
salama-object-file!
salama-reader!

122
lib/arm/arm_machine.rb
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@ -1,122 +0,0 @@
require_relative "instruction"
module Arm
# A Machines main responsibility in the framework is to instantiate Instructions
# Value functions are mapped to machines by concatenating the values class name + the methd name
# Example: IntegerValue.plus( value ) -> Machine.signed_plus (value )
# Also, shortcuts are created to easily instantiate Instruction objects.
# Example: pop -> StackInstruction.new( {:opcode => :pop}.merge(options) )
# Instructions work with options, so you can pass anything in, and the only thing the functions
# does is save you typing the clazz.new. It passes the function name as the :opcode
class ArmMachine
# conditions specify all the possibilities for branches. Branches are b + condition
# Example: beq means brach if equal.
# :al means always, so bal is an unconditional branch (but b() also works)
CONDITIONS = [:al ,:eq ,:ne ,:lt ,:le ,:ge,:gt ,:cs ,:mi ,:hi ,:cc ,:pl,:ls ,:vc ,:vs]
# here we create the shortcuts for the "standard" instructions, see above
# Derived machines may use own instructions and define functions for them if so desired
def self.init
[:push, :pop].each do |inst|
define_instruction_one(inst , StackInstruction)
end
[:adc, :add, :and, :bic, :eor, :orr, :rsb, :rsc, :sbc, :sub].each do |inst|
define_instruction_three(inst , LogicInstruction)
end
[:mov, :mvn].each do |inst|
define_instruction_two(inst , MoveInstruction)
end
[:cmn, :cmp, :teq, :tst].each do |inst|
define_instruction_two(inst , CompareInstruction)
end
[:strb, :str , :ldrb, :ldr].each do |inst|
define_instruction_three(inst , MemoryInstruction)
end
[:b, :call , :swi].each do |inst|
define_instruction_one(inst , CallInstruction)
end
# create all possible brach instructions, but the CallInstruction demangles the
# code, and has opcode set to :b and :condition_code set to the condition
CONDITIONS.each do |suffix|
define_instruction_one("b#{suffix}".to_sym , CallInstruction)
define_instruction_one("call#{suffix}".to_sym , CallInstruction)
end
end
def self.create_method(name, &block)
self.class.send(:define_method, name , &block)
end
def self.class_for clazz
my_module = self.class.name.split("::").first
clazz_name = clazz.name.split("::").last
if(my_module != Register )
module_class = eval("#{my_module}::#{clazz_name}") rescue nil
clazz = module_class if module_class
end
clazz
end
#defining the instruction (opcode, symbol) as an given class.
# the class is a Register::Instruction derived base class and to create machine specific function
# an actual machine must create derived classes (from this base class)
# These instruction classes must follow a naming pattern and take a hash in the contructor
# Example, a mov() opcode instantiates a Register::MoveInstruction
# for an Arm machine, a class Arm::MoveInstruction < Register::MoveInstruction exists, and it
# will be used to define the mov on an arm machine.
# This methods picks up that derived class and calls a define_instruction methods that can
# be overriden in subclasses
def self.define_instruction_one(inst , clazz , defaults = {} )
clazz = class_for(clazz)
create_method(inst) do |first , options = nil|
options = {} if options == nil
options.merge defaults
options[:opcode] = inst
first = Register::RegisterReference.convert(first)
clazz.new(first , options)
end
end
# same for two args (left right, from to etc)
def self.define_instruction_two(inst , clazz , defaults = {} )
clazz = self.class_for(clazz)
create_method(inst) do |left ,right , options = nil|
options = {} if options == nil
options.merge defaults
left = Register::RegisterReference.convert(left)
right = Register::RegisterReference.convert(right)
options[:opcode] = inst
clazz.new(left , right ,options)
end
end
# same for three args (result = left right,)
def self.define_instruction_three(inst , clazz , defaults = {} )
clazz = self.class_for(clazz)
create_method(inst) do |result , left ,right = nil , options = nil|
options = {} if options == nil
options.merge defaults
options[:opcode] = inst
result = Register::RegisterReference.convert(result)
left = Register::RegisterReference.convert(left)
right = Register::RegisterReference.convert(right)
clazz.new(result, left , right ,options)
end
end
end
end
Arm::ArmMachine.init
require_relative "passes/call_implementation"
require_relative "passes/branch_implementation"
require_relative "passes/syscall_implementation"
require_relative "passes/save_implementation"
require_relative "passes/transfer_implementation"
require_relative "passes/get_implementation"
require_relative "passes/set_implementation"
require_relative "passes/return_implementation"
require_relative "passes/constant_implementation"

127
lib/arm/constants.rb
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@ -1,127 +0,0 @@
module Arm
module Constants
OPCODES = {
:adc => 0b0101, :add => 0b0100,
:and => 0b0000, :bic => 0b1110,
:eor => 0b0001, :orr => 0b1100,
:rsb => 0b0011, :rsc => 0b0111,
:sbc => 0b0110, :sub => 0b0010,
# for these Rn is sbz (should be zero)
:mov => 0b1101,
:mvn => 0b1111,
# for these Rd is sbz and S=1
:cmn => 0b1011,
:cmp => 0b1010,
:teq => 0b1001,
:tst => 0b1000,
:b => 0b1010,
:call=> 0b1011
}
#return the bit patter that the cpu uses for the current instruction @attributes[:opcode]
def op_bit_code
bit_code = OPCODES[opcode]
bit_code or raise "no code found for #{opcode} #{inspect}"
end
#codition codes can be applied to many instructions and thus save branches
# :al => always , :eq => equal and so on
# eq mov if equal :moveq r1 r2 (also exists as function) will only execute
# if the last operation was 0
COND_CODES = {
:al => 0b1110, :eq => 0b0000,
:ne => 0b0001, :cs => 0b0010,
:mi => 0b0100, :hi => 0b1000,
:cc => 0b0011, :pl => 0b0101,
:ls => 0b1001, :vc => 0b0111,
:lt => 0b1011, :le => 0b1101,
:ge => 0b1010, :gt => 0b1100,
:vs => 0b0110
}
# return the bit pattern for the @attributes[:condition_code] variable,
# which signals the conditional code
def cond_bit_code
COND_CODES[@attributes[:condition_code]] or throw "no code found for #{@attributes[:condition_code]}"
end
REGISTERS = { 'r0' => 0, 'r1' => 1, 'r2' => 2, 'r3' => 3, 'r4' => 4, 'r5' => 5,
'r6' => 6, 'r7' => 7, 'r8' => 8, 'r9' => 9, 'r10' => 10, 'r11' => 11,
'r12' => 12, 'r13' => 13, 'r14' => 14, 'r15' => 15, 'a1' => 0, 'a2' => 1,
'a3' => 2, 'a4' => 3, 'v1' => 4, 'v2' => 5, 'v3' => 6, 'v4' => 7, 'v5' => 8,
'v6' => 9, 'rfp' => 9, 'sl' => 10, 'fp' => 11, 'ip' => 12, 'sp' => 13,
'lr' => 14, 'pc' => 15 }
def reg r_name
code = reg_code r_name
raise "no such register #{r_name}" unless code
Arm::Register.new(r_name.to_sym , code )
end
def reg_code r_name
raise "double r #{r_name}" if( :rr1 == r_name)
if r_name.is_a? ::Register::RegisterReference
r_name = r_name.symbol
end
if r_name.is_a? Fixnum
r_name = "r#{r_name}"
end
r = REGISTERS[r_name.to_s]
raise "no reg #{r_name}" if r == nil
r
end
def calculate_u8_with_rr(arg)
parts = arg.to_s(2).rjust(32,'0').scan(/^(0*)(.+?)0*$/).flatten
pre_zeros = parts[0].length
imm_len = parts[1].length
if ((pre_zeros+imm_len) % 2 == 1)
u8_imm = (parts[1]+'0').to_i(2)
imm_len += 1
else
u8_imm = parts[1].to_i(2)
end
if u8_imm.fits_u8?
# can do!
rot_imm = (pre_zeros+imm_len) / 2
if (rot_imm > 15)
return nil
end
return u8_imm | (rot_imm << 8)
else
return nil
end
end
#slighly wrong place for this code, but since the module gets included in instructions anyway . . .
# implement the barrel shifter on the operand (which is set up before as an integer)
def shift_handling
op = 0
#codes that one can shift, first two probably most common.
# l (in lsr) means logical, ie unsigned, a (in asr) is arithmetic, ie signed
shift_codes = {'lsl' => 0b000, 'lsr' => 0b010, 'asr' => 0b100, 'ror' => 0b110, 'rrx' => 0b110}
shift_codes.each do |short, bin|
long = "shift_#{short}".to_sym
if shif = @attributes[long]
# TODO delete this code, AFTER you understand it
# tests do pass without it, maybe need more tests ?
#if (shif.is_a?(Numeric))
# raise "should not be supported, check code #{inspect}"
# bin |= 0x1;
# shift = shif.register << 1
# end
raise "0 < shift <= 32 #{shif} #{inspect}" if (shif >= 32) or( shif < 0)
op |= shift(bin , 4 )
op |= shift(shif , 4+3)
break
end
end
return op
end
# arm intrucioons are pretty sensible, and always 4 bytes (thumb not supported)
def byte_length
4
end
end
end

46
lib/arm/instruction.rb
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@ -1,46 +0,0 @@
module Arm
# The arm machine has following instruction classes
# - Memory
# - Stack
# - Logic
# - Math
# - Control/Compare
# - Move
# - Call class Instruction
class Instruction
include Positioned
def initialize options
@attributes = options
end
attr_reader :attributes
def opcode
@attributes[:opcode]
end
# this is giving read access to the attributes hash via .attibute syntax
# so for an instruction pop you can write pop.opcode to get the :opcode attribute
# TODDO: review (don't remember what the "set_" stuff was for)
def method_missing name , *args , &block
return super unless (args.length <= 1) or block_given?
set , attribute = name.to_s.split("set_")
if set == ""
@attributes[attribute.to_sym] = args[0] || 1
return self
else
return super
end
return @attributes[name.to_sym]
end
end
end
require_relative "constants"
require_relative "instructions/call_instruction"
require_relative "instructions/compare_instruction"
require_relative "instructions/logic_instruction"
require_relative "instructions/memory_instruction"
require_relative "instructions/move_instruction"
require_relative "instructions/stack_instruction"

92
lib/arm/instructions/call_instruction.rb
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@ -1,92 +0,0 @@
module Arm
# There are only three call instructions in arm branch (b), call (bl) and syscall (swi)
# A branch could be called a jump as it has no notion of returning
# The pc is put into the link register to make a return possible
# a return is affected by moving the stored link register into the pc, effectively a branch
# swi (SoftWareInterrupt) or system call is how we call the kernel.
# in Arm the register layout is different and so we have to place the syscall code into register 7
# Registers 0-6 hold the call values as for a normal c call
class CallInstruction < Instruction
include Arm::Constants
def initialize(first, attributes)
super(attributes)
raise "no target" if first.nil?
@first = first
opcode = @attributes[:opcode].to_s
if opcode.length == 3 and opcode[0] == "b"
@attributes[:condition_code] = opcode[1,2].to_sym
@attributes[:opcode] = :b
end
if opcode.length == 6 and opcode[0] == "c"
@attributes[:condition_code] = opcode[4,2].to_sym
@attributes[:opcode] = :call
end
@attributes[:update_status] = 0
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
end
def assemble(io)
case @attributes[:opcode]
when :b, :call
arg = @first
if arg.is_a?(Virtual::Block) or arg.is_a?(Parfait::Method)
#relative addressing for jumps/calls
# but because of the arm "theoretical" 3- stage pipeline,
# we have to subtract 2 words (fetch/decode)
if(arg.is_a? Virtual::Block)
diff = arg.position - self.position - 8
else
# But, for methods, this happens to be the size of the object header,
# so there it balances out, but not blocks
# have to use the code, not the mthod object for methods
diff = arg.code.position - self.position
end
arg = diff
end
if (arg.is_a?(Numeric))
jmp_val = arg >> 2
packed = [jmp_val].pack('l')
# signed 32-bit, condense to 24-bit
# TODO add check that the value fits into 24 bits
io << packed[0,3]
else
raise "else not coded arg =\n#{arg.to_s[0..1000]}: #{inspect[0..1000]}"
end
io.write_uint8 op_bit_code | (COND_CODES[@attributes[:condition_code]] << 4)
when :swi
arg = @first
if (arg.is_a?(Numeric))
packed = [arg].pack('L')[0,3]
io << packed
io.write_uint8 0b1111 | (COND_CODES[@attributes[:condition_code]] << 4)
else
raise "invalid operand argument expected literal not #{arg} #{inspect}"
end
else
raise "Should not be the case #{inspect}"
end
end
def uses
if opcode == :call
@first.args.collect {|arg| arg.register }
else
[]
end
end
def assigns
if opcode == :call
[RegisterReference.new(RegisterMachine.instance.return_register)]
else
[]
end
end
def to_s
"#{opcode} #{@first} #{super}"
end
end
end

105
lib/arm/instructions/compare_instruction.rb
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@ -1,105 +0,0 @@
module Arm
class CompareInstruction < Instruction
include Arm::Constants
def initialize(left , right , attributes)
super(attributes)
@left = left
@right = right.is_a?(Fixnum) ? IntegerConstant.new(right) : right
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@operand = 0
@immediate = 0
@attributes[:update_status] = 1
@rn = left
@rd = :r0
end
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
rn = @rn
operand = @operand
immediate = @immediate
arg = @right
if arg.is_a?(Parfait::Object)
# do pc relative addressing with the difference to the instuction
# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
arg = arg.position - self.position - 8
rn = :pc
end
if( arg.is_a? Symbol )
arg = Register::RegisterReference.new( arg )
end
if (arg.is_a?(Numeric))
if (arg.fits_u8?)
# no shifting needed
operand = arg
immediate = 1
elsif (op_with_rot = calculate_u8_with_rr(arg))
operand = op_with_rot
immediate = 1
raise "hmm"
else
raise "cannot fit numeric literal argument in operand #{arg.inspect}"
end
elsif (arg.is_a?(Symbol) or arg.is_a?(::Register::RegisterReference))
operand = arg
immediate = 0
elsif (arg.is_a?(Arm::Shift))
rm_ref = arg.argument
immediate = 0
shift_op = {'lsl' => 0b000, 'lsr' => 0b010, 'asr' => 0b100,
'ror' => 0b110, 'rrx' => 0b110}[arg.type]
if (arg.type == 'ror' and arg.value.nil?)
# ror #0 == rrx
raise "cannot rotate by zero #{arg} #{inspect}"
end
arg1 = arg.value
if (arg1.is_a?(Virtual::IntegerConstant))
if (arg1.value >= 32)
raise "cannot shift by more than 31 #{arg1} #{inspect}"
end
shift_imm = arg1.value
elsif (arg1.is_a?(Arm::Register))
shift_op val |= 0x1;
shift_imm = arg1.number << 1
elsif (arg.type == 'rrx')
shift_imm = 0
end
operand = rm_ref | (shift_op << 4) | (shift_imm << 4+3)
else
raise "invalid operand argument #{arg.inspect} , #{inspect}"
end
instuction_class = 0b00 # OPC_DATA_PROCESSING
val = (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterReference)) ? reg_code(operand) : operand
val = 0 if val == nil
val = shift(val , 0)
raise inspect unless reg_code(@rd)
val |= shift(reg_code(@rd) , 12)
val |= shift(reg_code(rn) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 +1)
val |= shift(immediate , 12+4+4 +1+4)
val |= shift(instuction_class , 12+4+4 +1+4+1)
val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
io.write_uint32 val
end
def shift val , by
raise "Not integer #{val}:#{val.class} #{inspect}" unless val.is_a? Fixnum
val << by
end
def uses
ret = [@left.register ]
ret << @right.register unless @right.is_a? Constant
ret
end
def assigns
[]
end
def to_s
"#{opcode} #{@left} , #{@right} #{super}"
end
end
end

105
lib/arm/instructions/logic_instruction.rb
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@ -1,105 +0,0 @@
module Arm
class LogicInstruction < Instruction
include Arm::Constants
# result = left op right
#
# Logic instruction are your basic operator implementation. But unlike the (normal) code we write
# these Instructions must have "place" to write their results. Ie when you write 4 + 5 in ruby
# the result is sort of up in the air, but with Instructions the result must be assigned
def initialize(result , left , right , attributes = {})
super(attributes)
@result = result
@left = left
@right = right
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@operand = 0
raise "Left arg must be given #{inspect}" unless @left
@immediate = 0
end
attr_accessor :result , :left , :right
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
left = @left
operand = @operand
immediate = @immediate
right = @right
if @left.is_a?(Parfait::Object) or
@left.is_a?(Symbol) and !Register::RegisterReference.look_like_reg(@left)
# do pc relative addressing with the difference to the instuction
# 8 is for the funny pipeline adjustment (ie pointing to fetch and not execute)
right = @left.position - self.position - 8
raise "todo in direction #{right}" if( opcode == :add and right < 0 )
raise "No negatives implemented #{right} " if right < 0
left = :pc
end
if (right.is_a?(Numeric))
if (right.fits_u8?)
# no shifting needed
operand = right
immediate = 1
elsif (op_with_rot = calculate_u8_with_rr(right))
operand = op_with_rot
immediate = 1
else
#TODO this is copied from MoveInstruction, should rework
unless @extra
@extra = 1
#puts "RELINK L at #{self.position.to_s(16)}"
raise ::Register::LinkException.new("cannot fit numeric literal argument in operand #{right.inspect}")
end
# now we can do the actual breaking of instruction, by splitting the operand
first = right & 0xFFFFFF00
operand = calculate_u8_with_rr( first )
raise "no fit for #{right}" unless operand
immediate = 1
@extra = ArmMachine.add( result , result , (right & 0xFF) )
end
elsif (right.is_a?(Symbol) or right.is_a?(::Register::RegisterReference))
operand = reg_code(right) #integer means the register the integer is in (otherwise constant)
immediate = 0 # ie not immediate is register
else
raise "invalid operand argument #{right.inspect} , #{inspect}"
end
op = shift_handling
instuction_class = 0b00 # OPC_DATA_PROCESSING
val = shift(operand , 0)
val |= shift(op , 0) # any barral action, is already shifted
val |= shift(reg_code(@result) , 12)
val |= shift(reg_code(left) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 + 1)
val |= shift(immediate , 12+4+4 + 1+4)
val |= shift(instuction_class , 12+4+4 + 1+4+1)
val |= shift(cond_bit_code , 12+4+4 + 1+4+1+2)
io.write_uint32 val
# by now we have the extra add so assemble that
if(@extra)
@extra.assemble(io)
#puts "Assemble extra at #{val.to_s(16)}"
end
end
def shift val , by
raise "Not integer #{val}:#{val.class} #{inspect}" unless val.is_a? Fixnum
val << by
end
def byte_length
@extra ? 8 : 4
end
def uses
ret = []
ret << @left.register if @left and not @left.is_a? Constant
ret << @right.register if @right and not @right.is_a?(Constant)
ret
end
def assigns
[@result.register]
end
end
end

116
lib/arm/instructions/memory_instruction.rb
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@ -1,116 +0,0 @@
module Arm
# ADDRESSING MODE 2
# Implemented: immediate offset with offset=0
class MemoryInstruction < Instruction
include Arm::Constants
def initialize result , left , right = nil , attributes = {}
super(attributes)
@result = result
@left = left
@right = right
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@operand = 0
raise "alert" if right.is_a? Virtual::Block
@pre_post_index = 0 #P flag
@add_offset = 0 #U flag
@is_load = opcode.to_s[0] == "l" ? 1 : 0 #L (load) flag
end
def assemble(io )
# don't overwrite instance variables, to make assembly repeatable
rn = @rn
operand = @operand
add_offset = @add_offset
arg = @left
arg = arg.symbol if( arg.is_a? ::Register::RegisterReference )
#str / ldr are _serious instructions. With BIG possibilities not half are implemented
is_reg = arg.is_a?(::Register::RegisterReference)
if( arg.is_a?(Symbol) and not is_reg)
is_reg = (arg.to_s[0] == "r")
end
if (is_reg ) #symbol is register
rn = arg
if @right
operand = @right
#TODO better test, this operand integer (register) does not work. but sleep first
operand = operand.symbol if operand.is_a? ::Register::RegisterReference
unless( operand.is_a? Symbol)
#puts "operand #{operand.inspect}"
if (operand < 0)
add_offset = 0
#TODO test/check/understand
operand *= -1
else
add_offset = 1
end
if (@operand.abs > 4095)
raise "reference offset too large/small (max 4095) #{arg} #{inspect}"
end
end
end
elsif (arg.is_a?(Parfait::Object) or arg.is_a? Symbol ) #use pc relative
rn = :pc
operand = arg.position - self.position - 8 #stringtable is after code
add_offset = 1
if (operand.abs > 4095)
raise "reference offset too large/small (4095<#{operand}) #{arg} #{inspect}"
end
elsif( arg.is_a?(Numeric) )
#TODO untested brach, probably not working
raise "is this working ?? #{arg} #{inspect}"
@pre_post_index = 1
@rn = pc
@use_addrtable_reloc = true
@addrtable_reloc_target = arg
else
raise "invalid operand argument #{arg.inspect} #{inspect}"
end
#not sure about these 2 constants. They produce the correct output for str r0 , r1
# but i can't help thinking that that is because they are not used in that instruction and
# so it doesn't matter. Will see
add_offset = 1
# TODO to be continued
add_offset = 0 if @attributes[:add_offset]
@pre_post_index = 1
@pre_post_index = 0 if @attributes[:flaggie]
w = 0 #W flag
byte_access = opcode.to_s[-1] == "b" ? 1 : 0 #B (byte) flag
instuction_class = 0b01 # OPC_MEMORY_ACCESS
if (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterReference))
val = reg_code(operand)
@pre_post_index = 0
i = 1 # not quite sure about this, but it gives the output of as. read read read.
else
i = 0 #I flag (third bit)
val = operand
end
val = shift(val , 0 ) # for the test
val |= shift(reg_code(@result) , 12 )
val |= shift(reg_code(rn) , 12+4) #16
val |= shift(@is_load , 12+4 +4)
val |= shift(w , 12+4 +4+1)
val |= shift(byte_access , 12+4 +4+1+1)
val |= shift(add_offset , 12+4 +4+1+1+1)
val |= shift(@pre_post_index, 12+4 +4+1+1+1+1)#24
val |= shift(i , 12+4 +4+1+1+1+1 +1)
val |= shift(instuction_class,12+4 +4+1+1+1+1 +1+1)
val |= shift(cond_bit_code , 12+4 +4+1+1+1+1 +1+1+2)
io.write_uint32 val
end
def shift val , by
raise "Not integer #{val}:#{val.class} #{inspect}" unless val.is_a? Fixnum
val << by
end
def uses
ret = [@left.register ]
ret << @right.register unless @right.nil?
ret
end
def assigns
[@result.register]
end
end
end

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lib/arm/instructions/move_instruction.rb
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module Arm
class MoveInstruction < Instruction
include Arm::Constants
def initialize to , from , options = {}
super(options)
if( from.is_a?(Symbol) and Register::RegisterReference.look_like_reg(from) )
from = Register::RegisterReference.new(from)
end
@from = from
@to = to
raise "move must have from set #{inspect}" unless from
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@attributes[:opcode] = attributes[:opcode]
@operand = 0
@immediate = 0
@rn = :r0 # register zero = zero bit pattern
@extra = nil
end
attr_accessor :to , :from
# arm intructions are pretty sensible, and always 4 bytes (thumb not supported)
# but not all constants fit into the part of the instruction that is left after the instruction
# code, so large moves have to be split into two instructions.
# we handle this "transparently", just this instruction looks longer
# alas, full transparency is not achieved as we only know when to use 2 instruction once we
# know where the other object is, and that position is only set after code positions have been
# determined (in link) and so see below in assemble
def byte_length
@extra ? 8 : 4
end
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
rn = @rn
operand = @operand
immediate = @immediate
right = @from
if (right.is_a?(Numeric))
if (right.fits_u8?)
# no shifting needed
operand = right
immediate = 1
elsif (op_with_rot = calculate_u8_with_rr(right))
operand = op_with_rot
immediate = 1
else
# unfortunately i was wrong in thinking the pi is armv7. The good news is the code
# below implements the movw instruction (armv7 for moving a word) and works
#armv7 raise "Too big #{right} " if (right >> 16) > 0
#armv7 operand = (right & 0xFFF)
#armv7 immediate = 1
#armv7 rn = (right >> 12)
# a little STRANGE, that the armv7 movw (move a 2 byte word) is an old test opcode,
# but there it is
#armv7 @attributes[:opcode] = :tst
raise "No negatives implemented #{right} " if right < 0
# and so it continues: when we notice that the const doesn't fit, first time we raise an
# error,but set the extra flag, to say the instruction is now 8 bytes
# then on subsequent assemblies we can assemble
unless @extra
@extra = 1
#puts "RELINK M at #{self.position.to_s(16)}"
raise ::Register::LinkException.new("cannot fit numeric literal argument in operand #{right.inspect}")
end
# now we can do the actual breaking of instruction, by splitting the operand
first = right & 0xFFFFFF00
operand = calculate_u8_with_rr( first )
raise "no fit for #{right}" unless operand
immediate = 1
@extra = ArmMachine.add( to , to , (right & 0xFF) )
#TODO: this is still a hack, as it does not encode all possible values.
# The way it _should_ be done
# is to check that the first part is doabe with u8_with_rr AND leaves a u8 remainder
end
elsif( right.is_a? Register::RegisterReference)
operand = reg_code(right)
immediate = 0 # ie not immediate is register
else
raise "invalid operand argument #{right.class} , #{self.class}"
end
op = shift_handling
instuction_class = 0b00 # OPC_DATA_PROCESSING
val = shift(operand , 0)
val |= shift(op , 0) # any barrel action, is already shifted
val |= shift(reg_code(@to) , 12)
val |= shift(reg_code(rn) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 + 1)
val |= shift(immediate , 12+4+4 + 1+4)
val |= shift(instuction_class , 12+4+4 + 1+4+1)
val |= shift(cond_bit_code , 12+4+4 + 1+4+1+2)
io.write_uint32 val
# by now we have the extra add so assemble that
if(@extra)
@extra.assemble(io)
#puts "Assemble extra at #{val.to_s(16)}"
end
end
def shift val , by
raise "Not integer #{val}:#{val.class} in #{inspect}" unless val.is_a? Fixnum
val << by
end
def uses
@from.is_a?(Constant) ? [] : [@from.register]
end
def assigns
[@to.register]
end
end
end

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lib/arm/instructions/stack_instruction.rb
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module Arm
# ADDRESSING MODE 4
class StackInstruction < Instruction
include Arm::Constants
def initialize(first , attributes)
super(attributes)
@first = first
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@attributes[:opcode] = attributes[:opcode]
@operand = 0
@attributes[:update_status]= 0
@rn = :r0 # register zero = zero bit pattern
# downward growing, decrement before memory access
# official ARM style stack as used by gas
end
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
operand = @operand
if (@first.is_a?(Array))
operand = 0
@first.each do |r|
raise "nil register in push, index #{r}- #{inspect}" if r.nil?
operand = operand | (1 << reg_code(r))
end
else
raise "invalid operand argument #{inspect}"
end
write_base = 1
if (opcode == :push)
pre_post_index = 1
up_down = 0
is_pop = 0
else #pop
pre_post_index = 0
up_down = 1
is_pop = 1
end
instuction_class = 0b10 # OPC_STACK
cond = @attributes[:condition_code].is_a?(Symbol) ? COND_CODES[@attributes[:condition_code]] : @attributes[:condition_code]
@rn = :sp # sp register
#assemble of old
val = operand
val = val | (reg_code(@rn) << 16)
val = val | (is_pop << 16+4) #20
val = val | (write_base << 16+4+ 1)
val = val | (@attributes[:update_status] << 16+4+ 1+1)
val = val | (up_down << 16+4+ 1+1+1)
val = val | (pre_post_index << 16+4+ 1+1+1+1)#24
val = val | (instuction_class << 16+4+ 1+1+1+1 +2)
val = val | (cond << 16+4+ 1+1+1+1 +2+2)
io.write_uint32 val
end
def is_push?
opcode == :push
end
def is_pop?
!is_push?
end
def uses
is_push? ? regs : []
end
def assigns
is_pop? ? regs : []
end
def regs
@first
end
def to_s
"#{opcode} [#{@first.join(',') }] #{super}"
end
end
end

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lib/arm/machine_code.rb
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module Arm
class MachineCode
def function_call into , call
raise "Not CallSite #{call.inspect}" unless call.is_a? Virtual::CallSite
raise "Not linked #{call.inspect}" unless call.function
into.add_code call( call.function )
raise "No return type for #{call.function.name}" unless call.function.return_type
call.function.return_type
end
def main_start context
entry = Virtual::Block.new("main_entry",nil,nil)
entry.add_code mov( :fp , 0 )
entry.add_code call( context.function )
entry
end
def main_exit context
exit = Virtual::Block.new("main_exit",nil,nil)
syscall(exit , 1)
exit
end
def function_entry block, f_name
block.add_code push( [:lr] )
block
end
def function_exit entry , f_name
entry.add_code pop( [:pc] )
entry
end
# assumes string in standard receiver reg (r2) and moves them down for the syscall
def write_stdout function #, string
# TODO save and restore r0
function.mov( :r0 , 1 ) # 1 == stdout
function.mov( :r1 , receiver_register )
function.mov( receiver_register , :r3 )
syscall( function.insertion_point , 4 ) # 4 == write
end
# stop, do not return
def exit function #, string
syscall( function.insertion_point , 1 ) # 1 == exit
end
# the number (a Virtual::integer) is (itself) divided by 10, ie overwritten by the result
# and the remainder is overwritten (ie an out argument)
# not really a function, more a macro,
def div10 function, number , remainder
# Note about division: devision is MUCH more expensive than one would have thought
# And coding it is a bit of a mind leap: it's all about finding a a result that gets the
# remainder smaller than an int. i'll post some links sometime. This is from the arm manual
tmp = function.new_local
function.instance_eval do
sub( remainder , number , 10 )
sub( number , number , number , shift_lsr: 2)
add( number , number , number , shift_lsr: 4)
add( number , number , number , shift_lsr: 8)
add( number , number , number , shift_lsr: 16)
mov( number , number , shift_lsr: 3)
add( tmp , number , number , shift_lsl: 2)
sub( remainder , remainder , tmp , shift_lsl: 1 , update_status: 1)
add( number , number, 1 , condition_code: :pl )
add( remainder , remainder , 10 , condition_code: :mi )
end
end
def syscall block , num
# This is very arm specific, syscall number is passed in r7,
# other arguments like a c call ie 0 and up
sys = Virtual::Integer.new( Virtual::RegisterReference.new(SYSCALL_REG) )
ret = Virtual::Integer.new( Virtual::RegisterReference.new(RETURN_REG) )
block.add_code mov( sys , num )
block.add_code swi( 0 )
#todo should write type into r1 according to syscall
ret
end
end
end

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lib/arm/nodes.rb
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module Arm
class Shift
attr_accessor :type, :value, :argument
end
# Registers have off course a name (r1-16 for arm)
# but also refer to an address. In other words they can be an operand for instructions.
# Arm has addressing modes abound, and so can add to a register before actually using it
# If can actually shift or indeed shift what it adds, but not implemented
class Register
attr_accessor :name , :offset , :bits
def initialize name , bits
@name = name
@bits = bits
@offset = 0
end
# this is for the dsl, so we can write pretty code like r1 + 4
# when we want to access the next word (4) after r1
def + number
@offset = number
self
end
end
# maybe not used at all as code_gen::instruction raises if used.
# instead now using Arrays
class RegisterList
attr_accessor :registers
def initialize regs
@registers = regs
regs.each{ |reg| raise "not a reg #{sym} , #{reg}" unless reg.is_a?(Arm::Register) }
end
end
end

17
lib/arm/passes/branch_implementation.rb
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@ -1,17 +0,0 @@
module Arm
# This implements branch logic, which is simply assembler branch
#
# The only target for a call is a Block, so we just need to get the address for the code
# and branch to it.
#
class BranchImplementation
def run block
block.codes.dup.each do |code|
next unless code.is_a? Register::Branch
br = ArmMachine.b( code.block )
block.replace(code , br )
end
end
end
Virtual.machine.add_pass "Arm::BranchImplementation"
end

19
lib/arm/passes/call_implementation.rb
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module Arm
# This implements call logic, which is simply like a c call (not send, that involves lookup and all sorts)
#
# The only target for a call is a Method, so we just need to get the address for the code
# and call it.
#
# The only slight snag is that we would need to assemble before getting the address, but to assemble
# we'd have to have finished compiling. So we need a reference.
class CallImplementation
def run block
block.codes.dup.each do |code|
next unless code.is_a? Register::FunctionCall
call = ArmMachine.call( code.method )
block.replace(code , call )
end
end
end
Virtual.machine.add_pass "Arm::CallImplementation"
end

20
lib/arm/passes/constant_implementation.rb
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module Arm
class ConstantImplementation
def run block
block.codes.dup.each do |code|
next unless code.is_a? Register::LoadConstant
constant = code.constant
if constant.is_a?(Parfait::Object) or constant.is_a? Symbol
load = ArmMachine.add( code.register , constant )
else
load = ArmMachine.mov( code.register , code.constant )
end
block.replace(code , load )
#puts "replaced #{load.inspect.to_s[0..1000]}"
end
end
end
Virtual.machine.add_pass "Arm::ConstantImplementation"
end

14
lib/arm/passes/get_implementation.rb
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@ -1,14 +0,0 @@
module Arm
class GetImplementation
def run block
block.codes.dup.each do |code|
next unless code.is_a? Register::GetSlot
# times 4 because arm works in bytes, but vm in words
load = ArmMachine.ldr( code.register , code.array , 4 * code.index )
block.replace(code , load )
end
end
end
Virtual.machine.add_pass "Arm::GetImplementation"
end

13
lib/arm/passes/return_implementation.rb
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module Arm
class ReturnImplementation
def run block
block.codes.dup.each do |code|
next unless code.is_a? Register::FunctionReturn
load = ArmMachine.ldr( :pc , code.register , 4 * code.index )
block.replace(code , load )
end
end
end
Virtual.machine.add_pass "Arm::ReturnImplementation"
end

19
lib/arm/passes/save_implementation.rb
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module Arm
# Arm stores the return address in a register (not on the stack)
# The register is called link , or lr for short .
# Maybe because it provides the "link" back to the caller (?)
# the vm defines a register for the location, so we store it there.
class SaveImplementation
def run block
block.codes.dup.each do |code|
next unless code.is_a? Register::SaveReturn
store = ArmMachine.str( :lr , code.register , 4 * code.index )
block.replace(code , store )
end
end
end
Virtual.machine.add_pass "Arm::SaveImplementation"
end

15
lib/arm/passes/set_implementation.rb
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module Arm
class SetImplementation
def run block
block.codes.dup.each do |code|
next unless code.is_a? Register::SetSlot
# times 4 because arm works in bytes, but vm in words
# + 1 because of the type word
store = ArmMachine.str( code.register , code.array , 4 * code.index )
block.replace(code , store )
end
end
end
Virtual.machine.add_pass "Arm::SetImplementation"
end

39
lib/arm/passes/syscall_implementation.rb
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module Arm
class SyscallImplementation
CALLS_CODES = { :putstring => 4 , :exit => 1 }
def run block
block.codes.dup.each do |code|
next unless code.is_a? Register::Syscall
new_codes = []
int_code = CALLS_CODES[code.name]
raise "Not implemented syscall, #{code.name}" unless int_code
send( code.name , int_code , new_codes )
block.replace(code , new_codes )
end
end
def putstring int_code , codes
codes << ArmMachine.ldr( :r1 , Register.message_reg, 4 * Register.resolve_index(:message , :receiver))
codes << ArmMachine.add( :r1 , :r1 , 8 )
codes << ArmMachine.mov( :r0 , 1 ) # stdout == 1
codes << ArmMachine.mov( :r2 , 12 ) # String length, obvious TODO
syscall(int_code , codes )
end
def exit int_code , codes
syscall int_code , codes
end
private
# syscall is always triggered by swi(0)
# The actual code (ie the index of the kernel function) is in r7
def syscall int_code , codes
codes << ArmMachine.mov( :r7 , int_code )
codes << ArmMachine.swi( 0 )
end
end
Virtual.machine.add_pass "Arm::SyscallImplementation"
end

15
lib/arm/passes/transfer_implementation.rb
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@ -1,15 +0,0 @@
module Arm
class TransferImplementation
def run block
block.codes.dup.each do |code|
next unless code.is_a? Register::RegisterTransfer
# Register machine convention is from => to
# But arm has the receiver/result as the first
move = ArmMachine.mov( code.to , code.from)
block.replace(code , move )
end
end
end
Virtual.machine.add_pass "Arm::TransferImplementation"
end

29
test/arm/arm-helper.rb
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require_relative '../helper'
# try to test that the generation of basic instructions works
# one instruction at a time, reverse testing from objdump --demangle -Sfghxp
# tests are named as per assembler code, ie test_mov testing mov instruction
# adc add and bic eor orr rsb rsc sbc sub mov mvn cmn cmp teq tst b call bx swi strb
module ArmHelper
# need Assembler and a block (see those classes)
def setup
@machine = Arm::ArmMachine
end
# code is what the generator spits out, at least one instruction worth (.first)
# the op code is wat was witten as assembler in the first place and the binary result
# is reversed and in 4 bytes as ruby can only do 31 bits and so we can't test with just one int (?)
def assert_code code , op , should
assert_equal op , code.opcode
io = StringIO.new
code.assemble(io)
binary = io.string
assert_equal should.length , binary.length , "code length wrong for #{code.inspect}"
index = 0
binary.each_byte do |byte |
assert_equal should[index] , byte , "byte #{index} 0x#{should[index].to_s(16)} != 0x#{byte.to_s(16)}"
index += 1
end
end
end

30
test/arm/test_add.rb
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require_relative 'arm-helper'
class TestAdd < MiniTest::Test
include ArmHelper
def test_adc
code = @machine.adc :r1, :r3, :r5
assert_code code , :adc , [0x05,0x10,0xa3,0xe0] #e0 a3 10 05
end
def test_add
code = @machine.add :r1 , :r1, :r3
assert_code code , :add , [0x03,0x10,0x81,0xe0] #e0 81 10 03
end
def test_add_const
code = @machine.add :r1 , :r1, 0x22
assert_code code , :add , [0x22,0x10,0x81,0xe2] #e2 81 10 22
end
def test_add_const_shift
code = @machine.add( :r1 , :r1 , 0x22 , shift_lsr: 8)
assert_code code , :add , [0x22,0x14,0x81,0xe2] #e2 81 14 23
end
def test_add_lst
code = @machine.add( :r1 , :r2 , :r3 , shift_lsr: 8)
assert_code code , :add , [0x23,0x14,0x82,0xe0] #e0 82 14 23
end
def test_big_add
code = @machine.add :r1 , :r1, 0x220
assert_code code , :add , [0x22,0x1e,0x81,0xe2] #e2 81 1e 22
end
end

7
test/arm/test_all.rb
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require_relative "test_stack"
require_relative "test_control"
require_relative "test_logic"
require_relative "test_add"
require_relative "test_move"
require_relative "test_memory"
require_relative "test_compare"

22
test/arm/test_compare.rb
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@ -1,22 +0,0 @@
require_relative 'arm-helper'
class TestArmAsm < MiniTest::Test
include ArmHelper
def test_cmn
code = @machine.cmn :r1 , :r2
assert_code code , :cmn , [0x02,0x00,0x71,0xe1] #e1 71 00 02
end
def test_cmp
code = @machine.cmp :r1 , :r2
assert_code code , :cmp , [0x02,0x00,0x51,0xe1] #e1 51 00 02
end
def test_teq
code = @machine.teq :r1 , :r2
assert_code code , :teq , [0x02,0x00,0x31,0xe1] #e1 31 00 02
end
def test_tst
code = @machine.tst :r1 , :r2
assert_code code , :tst , [0x02,0x00,0x11,0xe1] #e1 11 00 02
end
end

21
test/arm/test_control.rb
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require_relative 'arm-helper'
class TestControl < MiniTest::Test
include ArmHelper
def test_b
# the address is what an assembler calculates (a signed number for the amount of instructions),
# ie the relative (to pc) address -8 (pipeline) /4 so save space
# so the cpu adds the value*4 and starts loading that (load, decode, execute)
code = @machine.b -4 #this jumps to the next instruction
assert_code code , :b , [0xff,0xff,0xff,0xea] #ea ff ff fe
end
def test_call #see comment above. bx not implemented (as it means into thumb, and no thumb here)
code = @machine.call -4 ,{} #this jumps to the next instruction
assert_code code , :call, [0xff,0xff,0xff,0xeb] #ea ff ff fe
end
def test_swi
code = @machine.swi 0x05
assert_code code , :swi , [0x05,0x00,0x00,0xef]#ef 00 00 05
end
end

42
test/arm/test_logic.rb
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require_relative 'arm-helper'
class TestLogic < MiniTest::Test
include ArmHelper
def test_and # inst eval doesn't really work with and
code = @machine.and( :r1 , :r2 , :r3)
assert_code code , :and , [0x03,0x10,0x02,0xe0] #e0 01 10 03
end
def test_bic
code = @machine.bic :r2 , :r2 , :r3
assert_code code , :bic , [0x03,0x20,0xc2,0xe1] #e3 c2 20 44
end
def test_eor
code = @machine.eor :r2 , :r2 , :r3
assert_code code , :eor , [0x03,0x20,0x22,0xe0] #e0 22 20 03
end
def test_rsb
code = @machine.rsb :r1 , :r2 , :r3
assert_code code , :rsb , [0x03,0x10,0x62,0xe0]#e0 62 10 03
end
def test_rsc
code = @machine.rsc :r2 , :r3 , :r4
assert_code code , :rsc , [0x04,0x20,0xe3,0xe0]#e0 e3 20 04
end
def test_sbc
code = @machine.sbc :r3, :r4 , :r5
assert_code code , :sbc , [0x05,0x30,0xc4,0xe0]#e0 c4 30 05
end
def test_sub
code = @machine.sub :r2, :r0, 1
assert_code code, :sub , [0x01,0x20,0x40,0xe2] #e2 40 20 01
end
def test_subs
code = @machine.sub :r2, :r2, 1 , update_status: 1
assert_code code, :sub , [0x01,0x20,0x52,0xe2] #e2 52 20 01
end
def test_orr
code = @machine.orr :r2 , :r2 , :r3
assert_code code , :orr , [0x03,0x20,0x82,0xe1] #e1 82 20 03
end
end

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test/arm/test_memory.rb
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require_relative 'arm-helper'
class TestMemory < MiniTest::Test
include ArmHelper
def test_ldr
code = @machine.ldr :r0, :r0
assert_code code, :ldr , [0x00,0x00,0x90,0xe5] #e5 90 00 00
end
def test_ldr_const_offset
code = @machine.ldr :r0, :r0 , 4
assert_code code, :ldr , [0x04,0x00,0x90,0xe5] #e5 90 00 04
end
def test_ldr_reg_offset
code = @machine.ldr :r0, :r1 , :r2
assert_code code, :ldr , [0x02,0x00,0x91,0xe6] #e6 91 00 02
end
def test_ldrb
code = @machine.ldrb :r0, :r0
assert_code code, :ldrb , [0x00,0x00,0xd0,0xe5] #e5 d0 00 00
end
def test_str
code = @machine.str :r0, :r1
assert_code code, :str , [0x00,0x00,0x81,0xe5] #e5 81 00 00
end
def test_strb_add
code = @machine.strb :r0, :r1 , 1 , flaggie: 1
assert_code code, :strb , [0x01,0x00,0xc1,0xe4] #e4 c1 00 01
end
def test_strb
code = @machine.strb :r0, :r0
assert_code code, :strb , [0x00,0x00,0xc0,0xe5] #e5 c0 00 00
end
end

35
test/arm/test_move.rb
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require_relative 'arm-helper'
class TestMoves < MiniTest::Test
include ArmHelper
def test_mov
code = @machine.mov :r1, 5
assert_code code , :mov , [0x05,0x10,0xa0,0xe3] #e3 a0 10 05
end
def test_mov_pc
code = @machine.mov :pc, 5
assert_code code , :mov , [0x05,0xf0,0xa0,0xe3] #e3 a0 f0 06
end
def test_mov_256
code = @machine.mov :r1, 256
assert_code code , :mov , [0x01,0x1c,0xa0,0xe3] #e3 a0 1c 01
end
def test_mov_max_128
code = @machine.mov :r1, 128
assert_code code , :mov , [0x80,0x10,0xa0,0xe3] #e3 a0 10 80
end
def test_mov_big
code = @machine.mov :r0, 0x222 # is not 8 bit and can't be rotated by the arm system in one instruction
code.set_position(0)
begin # mov 512(0x200) = e3 a0 0c 02 add 34(0x22) = e2 80 00 22
assert_code code , :mov , [ 0x02,0x0c,0xa0,0xe3 , 0x22,0x00,0x80,0xe2]
rescue Register::LinkException
retry
end
end
def test_mvn
code = @machine.mvn :r1, 5
assert_code code , :mvn , [0x05,0x10,0xe0,0xe3] #e3 e0 10 05
end
end

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test/arm/test_stack.rb
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require_relative 'arm-helper'
class TestStack < MiniTest::Test
include ArmHelper
def test_push
code = @machine.push [:lr]
assert_code code , :push , [0x00,0x40,0x2d,0xe9] #e9 2d 40 00
end
def test_push_three
code = @machine.push [:r0,:r1,:lr]
assert_code code , :push , [0x03,0x40,0x2d,0xe9] #e9 2d 40 03
end
def test_push_no_link
code = @machine.push [:r0,:r1,:r2 ,:r3,:r4,:r5]
assert_code code , :push , [0x3f,0x00,0x2d,0xe9] #e9 2d 00 3f
end
def test_pop
code = @machine.pop [:pc]
assert_code code , :pop , [0x00,0x80,0xbd,0xe8] #e8 bd 80 00
end
def test_pop_three
code = @machine.pop [:r0,:r1,:pc]
assert_code code , :pop , [0x03,0x80,0xbd,0xe8] #e8 bd 80 03
end
def test_pop_no_pc
code = @machine.pop [:r0,:r1,:r2 ,:r3,:r4,:r5]
assert_code code , :pop , [0x3f,0x00,0xbd,0xe8] #e8 bd 00 3f
end
end

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test/test_all.rb
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# All working tests (ahm), still working on the others, so no use to be constantly reminded
require_relative "arm/test_all"
require "parfait/test_all"
require_relative "parfait/test_all"
require_relative "virtual/test_all"