Fix risc layer from cc changes

This commit is contained in:
2019-08-23 10:20:39 +03:00
parent 7ca3599c5a
commit ec1e8c8f3a
10 changed files with 92 additions and 93 deletions

View File

@ -25,7 +25,7 @@ module Risc
assert_equal 0 , Position.get(@linker.cpu_init).at
end
def test_cpu_at
assert_equal "0x576c" , Position.get(@linker.cpu_init.first).to_s
assert_equal "0x5edc" , Position.get(@linker.cpu_init.first).to_s
end
def test_cpu_label
assert_equal Position , Position.get(@linker.cpu_init.first).class