remove some more add_xx functions

also load labels by dsl now
This commit is contained in:
Torsten Ruger 2018-08-14 20:24:48 +03:00
parent 520dc7b41f
commit e953cc90d5
5 changed files with 14 additions and 10 deletions

View File

@ -139,9 +139,8 @@ module Risc
# for computationally building code (ie writing assembler) these short cuts # for computationally building code (ie writing assembler) these short cuts
# help to instantiate risc instructions and add them immediately # help to instantiate risc instructions and add them immediately
[:label, :reg_to_slot , :slot_to_reg , :load_constant, :load_data, [ :slot_to_reg , :load_constant, :load_data,
:function_return , :function_call, :op , :transfer ].each do |method|
:transfer , :reg_to_slot , :byte_to_reg , :reg_to_byte].each do |method|
define_method("add_#{method}".to_sym) do |*args| define_method("add_#{method}".to_sym) do |*args|
if not @source_used if not @source_used
args[0] = @source args[0] = @source

View File

@ -106,7 +106,7 @@ module Risc
def add_receiver(builder) def add_receiver(builder)
message = Risc.message_reg message = Risc.message_reg
ret_type = builder.compiler.receiver_type ret_type = builder.compiler.receiver_type
ret = builder.compiler.use_reg( ret_type ) ret = builder.compiler.use_reg( ret_type ).set_builder(builder)
builder.add_slot_to_reg(" load self" , message , :receiver , ret ) builder.add_slot_to_reg(" load self" , message , :receiver , ret )
builder.add_slot_to_reg( "int -> fix" , ret , Parfait::Integer.integer_index , ret) builder.add_slot_to_reg( "int -> fix" , ret , Parfait::Integer.integer_index , ret)
return ret return ret
@ -167,7 +167,7 @@ module Risc
builder.add_code Risc.op( s , :+ , q , tmp ) builder.add_code Risc.op( s , :+ , q , tmp )
builder.add_new_int(s,q , tmp) builder.add_new_int(s,q , tmp)
builder.add_reg_to_slot( s , tmp , Risc.message_reg , :return_value) builder.build{ message[:return_value] << tmp }
compiler.add_mom( Mom::ReturnSequence.new) compiler.add_mom( Mom::ReturnSequence.new)
return compiler return compiler

View File

@ -70,11 +70,11 @@ module Risc
end end
exit_label = Risc.label(compiler.source , "#{compiler.receiver_type.object_class.name}.#{compiler.source.name}" ) exit_label = Risc.label(compiler.source , "#{compiler.receiver_type.object_class.name}.#{compiler.source.name}" )
ret_tmp = compiler.use_reg(:Label) ret_tmp = compiler.use_reg(:Label).set_builder(builder)
builder.build do builder.build do
add_load_constant("__init__ load return", exit_label , ret_tmp) ret_tmp << exit_label
add_reg_to_slot("__init__ store return", ret_tmp , Risc.message_reg , :return_address) message[:return_address] << ret_tmp
add_function_call( "__init__ issue call" , Parfait.object_space.get_main) add_code Risc.function_call( "__init__ issue call" , Parfait.object_space.get_main)
add_code exit_label add_code exit_label
end end
compiler.reset_regs compiler.reset_regs

View File

@ -134,7 +134,7 @@ module Risc
# - an RValue, resulting in an SlotToReg # - an RValue, resulting in an SlotToReg
def <<( right ) def <<( right )
case right case right
when Parfait::Object , Symbol when Parfait::Object , Symbol , Label
ins = Risc.load_constant("#{right.class} to #{self.type}" , right , self) ins = Risc.load_constant("#{right.class} to #{self.type}" , right , self)
when Fixnum when Fixnum
ins = Risc.load_data("#{right.class} to #{self.type}" , right , self) ins = Risc.load_data("#{right.class} to #{self.type}" , right , self)

View File

@ -31,6 +31,11 @@ module Risc
move = @r1 << :puts move = @r1 << :puts
assert_equal LoadConstant , move.class assert_equal LoadConstant , move.class
end end
def test_load_label
label = Risc::Label.new("HI","ho" , FakeAddress.new(0))
move = @r1 << label
assert_equal LoadConstant , move.class
end
def test_transfer def test_transfer
transfer = @r0 << @r1 transfer = @r0 << @r1
assert_equal Transfer , transfer.class assert_equal Transfer , transfer.class