bit more regs, bit more resets

This commit is contained in:
Torsten Ruger 2018-04-08 22:29:08 +03:00
parent 33ffcf1d88
commit e5d014b936
4 changed files with 6 additions and 4 deletions

View File

@ -71,6 +71,7 @@ module Risc
add_function_call( "__init__ issue call" , Parfait.object_space.get_main , ret_tmp)
add_code exit_label
end
compiler.reset_regs
emit_syscall( builder , :exit )
return compiler.method
end

View File

@ -50,6 +50,7 @@ module Risc
#puts "adding mom #{instruction.to_s}:#{instruction.next.to_s}"
risc = instruction.to_risc( self )
add_code(risc)
reset_regs
#puts "adding risc #{risc.to_s}:#{risc.next.to_s}"
instruction = instruction.next
end

View File

@ -47,7 +47,7 @@ module Risc
#helper method to calculate with register symbols
def next_reg_use( type , value = nil )
int = @symbol[1,3].to_i
raise "No more registers #{self}" if int > 8
raise "No more registers #{self}" if int > 11
sym = "r#{int + 1}".to_sym
RiscValue.new( sym , type, value)
end
@ -64,14 +64,14 @@ module Risc
# - an RValue, resulting in an SlotToReg
def <<( right )
case right
when Parfait::Object
when Parfait::Object , Symbol
ins = Risc.load_constant("#{right.class} to #{self.type}" , right , self)
when RiscValue
ins = Risc.transfer("#{right.type} to #{self.type}" , right , self)
when RValue
ins = Risc.slot_to_reg("#{right.register.type}[#{right.index}] -> #{self.type}" , right.register , right.index , self)
else
raise "not implemented"
raise "not implemented for #{right.class}:#{right}"
end
builder.add_code(ins) if builder
return ins

View File

@ -47,7 +47,7 @@ module Risc
classes = []
tick = 1
begin
while true and (classes.length < 200)
while true and (classes.length < 300)
cl = ticks(1).class
tick += 1
classes << cl