bit more regs, bit more resets

This commit is contained in:
Torsten Ruger
2018-04-08 22:29:08 +03:00
parent 33ffcf1d88
commit e5d014b936
4 changed files with 6 additions and 4 deletions

View File

@ -47,7 +47,7 @@ module Risc
classes = []
tick = 1
begin
while true and (classes.length < 200)
while true and (classes.length < 300)
cl = ticks(1).class
tick += 1
classes << cl