adds a lot of to_ssss
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@ -28,6 +28,9 @@ module Mom
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@arguments.each{|a| raise "args not SlotLoad #{a}" unless a.is_a?(SlotLoad)}
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@arguments.each{|a| raise "args not SlotLoad #{a}" unless a.is_a?(SlotLoad)}
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end
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end
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def to_s
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"ArgumentTransfer " + ([@receiver] + @arguments).join(",")
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end
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def to_risc(compiler)
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def to_risc(compiler)
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transfer = SlotLoad.new([:message , :next_message , :receiver] , @receiver, self).to_risc(compiler)
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transfer = SlotLoad.new([:message , :next_message , :receiver] , @receiver, self).to_risc(compiler)
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compiler.reset_regs
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compiler.reset_regs
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@ -18,6 +18,12 @@ module Mom
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@cache_entry = Parfait::CacheEntry.new(type, method)
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@cache_entry = Parfait::CacheEntry.new(type, method)
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end
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end
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def to_s
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str = "DynamicCall "
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str += cache_entry.cached_method&.name if cache_entry
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str
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end
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# One could almost think that one can resolve this to a Risc::FunctionCall
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# One could almost think that one can resolve this to a Risc::FunctionCall
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# (which btw resolves to a simple jump), alas, the FunctionCall, like all other
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# (which btw resolves to a simple jump), alas, the FunctionCall, like all other
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# jumping, resolves the address at compile time.
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# jumping, resolves the address at compile time.
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@ -14,6 +14,10 @@ module Mom
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@name = name
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@name = name
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end
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end
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def to_s
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"Label: #{name}"
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end
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# A Mom::Label converts one2one to a Risc::Label. So in a way it could not be more
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# A Mom::Label converts one2one to a Risc::Label. So in a way it could not be more
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# simple.
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# simple.
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# Alas, since almost by definition several roads lead to this label, all those
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# Alas, since almost by definition several roads lead to this label, all those
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@ -16,6 +16,10 @@ module Mom
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@left , @right = left , right
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@left , @right = left , right
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end
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end
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def to_s
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"NotSameCheck: #{left}:#{right}"
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end
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# basically move both left and right values into register
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# basically move both left and right values into register
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# subtract them and see if IsZero comparison
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# subtract them and see if IsZero comparison
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def to_risc(compiler)
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def to_risc(compiler)
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@ -31,6 +31,9 @@ module Mom
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moves << Risc::FunctionReturn.new(self, return_address)
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moves << Risc::FunctionReturn.new(self, return_address)
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end
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end
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def to_s
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"ReturnSequence"
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end
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end
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end
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end
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end
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@ -14,6 +14,9 @@ module Mom
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@method = method
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@method = method
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end
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end
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def to_s
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"SimpleCall #{@method.name}"
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end
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# To call the method, we determine the jumpable address (method.binary), move that
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# To call the method, we determine the jumpable address (method.binary), move that
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# into a register and issue a FunctionCall
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# into a register and issue a FunctionCall
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#
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#
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@ -34,6 +34,10 @@ module Mom
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@original_source = original_source || self
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@original_source = original_source || self
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end
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end
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def to_s
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"SlotLoad #{right} -> #{left}"
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end
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def to_risc(compiler)
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def to_risc(compiler)
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const = @right.to_register(compiler , original_source)
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const = @right.to_register(compiler , original_source)
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left_slots = @left.slots
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left_slots = @left.slots
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@ -83,6 +87,23 @@ module Mom
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raise "No slots #{object}" unless slots
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raise "No slots #{object}" unless slots
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end
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end
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def to_s
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names = [known_name] + @slots
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"[#{names.join(',')}]"
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end
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def known_name
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case known_object
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when Constant , Parfait::Object
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known_object.class.short_name
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when Risc::Label
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known_object.to_s
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when Symbol
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known_object
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else
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"unknown"
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end
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end
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def to_register(compiler, instruction)
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def to_register(compiler, instruction)
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type = known_object.respond_to?(:ct_type) ? known_object.ct_type : :Object
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type = known_object.respond_to?(:ct_type) ? known_object.ct_type : :Object
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right = compiler.use_reg( type )
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right = compiler.use_reg( type )
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@ -13,5 +13,8 @@ module Parfait
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@cached_type = type
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@cached_type = type
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@cached_method = method
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@cached_method = method
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end
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end
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def to_s
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"CacheEntry" + "#{cached_method&.name}"
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end
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end
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end
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end
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end
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@ -6,7 +6,11 @@ class String
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self[0].capitalize + self[1..-1]
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self[0].capitalize + self[1..-1]
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end
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end
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end
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end
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class Class
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def short_name
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self.name.split("::").last
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end
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end
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# The RiscMachine, is an abstract machine with registers. Think of it as an arm machine with
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# The RiscMachine, is an abstract machine with registers. Think of it as an arm machine with
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# normal instruction names. It is not however an abstraction of existing hardware, but only
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# normal instruction names. It is not however an abstraction of existing hardware, but only
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