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while assembles, now for some nice assmbler reading

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This commit is contained in:
Torsten Ruger 2014-05-14 12:54:23 +03:00
parent a5b4f3d9ad
commit d8d536aa2c
4 changed files with 21 additions and 15 deletions
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4
lib/arm/arm_machine.rb
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@ -16,12 +16,12 @@ module Arm
end end
def integer_plus block , left , right def integer_plus block , left , right
block.add_code add(:left => left , :right => right ) block.add_code add(:left => left , :right => left , :extra => :right )
left left
end end
def integer_minus block , left , right def integer_minus block , left , right
block.add_code sub(:left => left , :right => right ) block.add_code sub(:left => left , :right => left , :extra => :right )
left left
end end

2
lib/arm/call_instruction.rb
View File

@ -34,7 +34,7 @@ module Arm
if( arg.is_a? Fixnum ) #HACK to not have to change the code just now if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
arg = Vm::IntegerConstant.new( arg ) arg = Vm::IntegerConstant.new( arg )
end end
if arg.is_a? Vm::Block if arg.is_a?(Vm::Block) or arg.is_a?(Vm::Function)
diff = arg.position - self.position - 8 diff = arg.position - self.position - 8
arg = Vm::IntegerConstant.new(diff) arg = Vm::IntegerConstant.new(diff)
end end

3
lib/arm/constants.rb
View File

@ -56,6 +56,9 @@ module Arm
Arm::Register.new(name.to_sym , code ) Arm::Register.new(name.to_sym , code )
end end
def reg_code name def reg_code name
if name.is_a? Vm::Word
name = "r#{name.register}"
end
REGISTERS[name.to_s] REGISTERS[name.to_s]
end end

27
lib/arm/logic_helper.rb
View File

@ -31,9 +31,6 @@ module Arm
if( arg.is_a? Fixnum ) #HACK to not have to change the code just now if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
arg = Vm::IntegerConstant.new( arg ) arg = Vm::IntegerConstant.new( arg )
end end
if( arg.is_a? Vm::Integer ) #HACK to not have to change the code just now
arg = Vm::IntegerConstant.new( arg.value )
end
if (arg.is_a?(Vm::IntegerConstant)) if (arg.is_a?(Vm::IntegerConstant))
if (arg.integer.fits_u8?) if (arg.integer.fits_u8?)
# no shifting needed # no shifting needed
@ -45,7 +42,7 @@ module Arm
else else
raise "cannot fit numeric literal argument in operand #{arg.inspect}" raise "cannot fit numeric literal argument in operand #{arg.inspect}"
end end
elsif (arg.is_a?(Symbol)) elsif (arg.is_a?(Symbol) or arg.is_a?(Vm::Integer))
@operand = arg @operand = arg
@i = 0 @i = 0
elsif (arg.is_a?(Arm::Shift)) elsif (arg.is_a?(Arm::Shift))
@ -79,16 +76,22 @@ module Arm
def assemble(io) def assemble(io)
build build
instuction_class = 0b00 # OPC_DATA_PROCESSING instuction_class = 0b00 # OPC_DATA_PROCESSING
val = @operand.is_a?(Symbol) ? reg_code(@operand) : @operand val = (@operand.is_a?(Symbol) or @operand.is_a?(Vm::Integer)) ? reg_code(@operand) : @operand
val = 0 if val == nil
val = shift(val , 0)
raise inspect unless reg_code(@rd) raise inspect unless reg_code(@rd)
val |= (reg_code(@rd) << 12) val |= shift(reg_code(@rd) , 12)
val |= (reg_code(@rn) << 12+4) val |= shift(reg_code(@rn) , 12+4)
val |= (@attributes[:update_status_flag] << 12+4+4)#20 val |= shift(@attributes[:update_status_flag] , 12+4+4)#20
val |= (op_bit_code << 12+4+4 +1) val |= shift(op_bit_code , 12+4+4 +1)
val |= (@i << 12+4+4 +1+4) val |= shift(@i , 12+4+4 +1+4)
val |= (instuction_class << 12+4+4 +1+4+1) val |= shift(instuction_class , 12+4+4 +1+4+1)
val |= (cond_bit_code << 12+4+4 +1+4+1+2) val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
io.write_uint32 val io.write_uint32 val
end end
def shift val , by
raise "Not integer #{val}:#{val.class}" unless val.is_a? Fixnum
val << by
end
end end
end end