while compiles. jo

2014-05-14 12:02:54 +03:00
parent d50c38f5ad
commit d6b5d46165
5 changed files with 18 additions and 11 deletions
--- a/lib/arm/arm_machine.rb
+++ b/lib/arm/arm_machine.rb
@ -26,10 +26,15 @@ module Arm
    end

    def integer_load block , left , right
-      reg = "r#{left.register}".to_sym
-      block.add_code mov( :left => reg , :right => right )
+      block.add_code mov( :left => left , :right => right )
      left 
    end
+
+    def integer_move block , left , right
+      block.add_code mov( :left => left , :right => right )
+      left 
+    end
+
    def string_load block ,  str_lit , reg
      block.add_code add( :left => "r#{reg}".to_sym   , :extra => str_lit )   #right is pc, implicit
        #second arg is a hack to get the stringlength without coding