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Fix all but one test

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Riples upon riples. The one left looks like the genuine article
This commit is contained in:
Torsten Rüger
2019-08-16 21:43:54 +03:00
parent 7c91a08d5b
commit d3f3c91ae5
23 changed files with 223 additions and 179 deletions
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11
test/mom/test_return_call.rb
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@ -7,18 +7,17 @@ module Risc
def setup
super
@input = "return 5.div4"
@expect = [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg,
FunctionCall, Label, SlotToReg, SlotToReg, RegToSlot,
SlotToReg, SlotToReg, RegToSlot, Branch]
@expect = [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot, #4
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg, #9
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, #14
FunctionCall, Label, SlotToReg, RegToSlot, Branch] #19
end
def test_return_instructions
assert_nil msg = check_nil , msg
end
def test_function_return
produced = produce_body.next(23)
produced = produce_body.next(19)
assert_equal Branch , produced.class
assert_equal "return_label" , produced.label.name
end

27
test/mom/test_while_cmp.rb
View File

@ -7,14 +7,13 @@ module Risc
def setup
super
@input = "while(5 > 0) ; @a = true; end"
@expect = [Label, LoadConstant, LoadConstant, SlotToReg, SlotToReg,
RegToSlot, RegToSlot, RegToSlot, RegToSlot, LoadConstant,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg,
FunctionCall, Label, SlotToReg, SlotToReg, RegToSlot,
SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsZero,
LoadConstant, OperatorInstruction, IsZero, LoadConstant, SlotToReg,
RegToSlot, Branch, Label]
@expect = [Label, LoadConstant, LoadConstant, SlotToReg, SlotToReg, #4
RegToSlot, RegToSlot, RegToSlot, RegToSlot, LoadConstant, #9
SlotToReg, RegToSlot, LoadConstant, SlotToReg, SlotToReg, #14
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, #19
FunctionCall, Label, SlotToReg, LoadConstant, OperatorInstruction, #24
IsZero, LoadConstant, OperatorInstruction, IsZero, LoadConstant, #29
SlotToReg, RegToSlot, Branch, Label] #34
end
def test_while_instructions
@ -39,19 +38,19 @@ module Risc
end
def test_false_check
produced = produce_body
assert_equal Risc::IsZero , produced.next(29).class
assert produced.next(29).label.name.start_with?("merge_label") , produced.next(29).label.name
assert_equal Risc::IsZero , produced.next(25).class
assert produced.next(25).label.name.start_with?("merge_label") , produced.next(25).label.name
end
def test_nil_load
produced = produce_body
assert_equal Risc::LoadConstant , produced.next(30).class
assert_equal Parfait::NilClass , produced.next(30).constant.class
assert_equal Risc::LoadConstant , produced.next(29).class
assert_equal Parfait::TrueClass , produced.next(29).constant.class
end
def test_back_jump # should jump back to condition label
produced = produce_body
assert_equal Risc::Branch , produced.next(36).class
assert_equal produced , produced.next(36).label
assert_equal Risc::Branch , produced.next(32).class
assert_equal produced.name , produced.next(32).label.name
end
end