Fix set_internal_byte registers

This commit is contained in:
2020-03-11 22:54:44 +02:00
parent 2656bfacb2
commit d125a1528a
2 changed files with 16 additions and 19 deletions

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@ -18,20 +18,21 @@ module SlotMachine
assert_equal 20 , @method.to_risc.risc_instructions.length
end
def test_all
assert_slot_to_reg risc(1),:r0 , 2 , :r1
assert_slot_to_reg risc(2),:r0 , 10 , :r2
assert_reg_to_slot risc(3) , :r2 , :r0 , 5
assert_slot_to_reg risc(4),:r0 , 9 , :r3
assert_slot_to_reg risc(5),:r3 , 2 , :r3
assert_slot_to_reg risc(6),:r2 , 2 , :r2
assert_equal Risc::RegToByte , risc(7).class
assert_slot_to_reg risc(8),:r0 , 5 , :r2
assert_reg_to_slot risc(9) , :r2 , :r0 , 5
assert_branch risc(10) , "return_label"
assert_label risc(11) , "return_label"
assert_slot_to_reg 1 ,:message , 10 , "message.arg2"
assert_reg_to_slot 2 , "message.arg2" , :message , 5
assert_slot_to_reg 3 ,:message , 9 , "message.arg1"
assert_slot_to_reg 4 ,"message.arg1" , 2 , "message.arg1.data_1"
assert_slot_to_reg 5 ,:message , 2 , "message.receiver"
assert_slot_to_reg 6 ,:message , 10 , "message.arg2"
assert_slot_to_reg 7 ,"message.arg2" , 2 , "message.arg2.data_1"
assert_equal Risc::RegToByte , risc(8).class
assert_slot_to_reg 9 ,:message , 5 , "message.return_value"
assert_reg_to_slot 10 , "message.return_value" , :message , 5
assert_branch 11 , "return_label"
assert_label 12 , "return_label"
end
def test_return
assert_return(11)
assert_return(12)
end
end
end