fix object loading
by (ahem) copying the code from MoveInst.
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@ -27,10 +27,13 @@ module Arm
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immediate = @immediate
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immediate = @immediate
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right = @right
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right = @right
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if @left.is_a?(Parfait::Object)
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if @left.is_a?(Parfait::Object) or
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@left.is_a?(Symbol) and !Register::RegisterReference.look_like_reg(@left)
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# do pc relative addressing with the difference to the instuction
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# do pc relative addressing with the difference to the instuction
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# 8 is for the funny pipeline adjustment (ie pointing to fetch and not execute)
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# 8 is for the funny pipeline adjustment (ie pointing to fetch and not execute)
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right = @left.position - self.position - 8
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right = @left.position - self.position
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raise "todo in direction #{right}" if( opcode == :add and right < 0 )
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raise "No negatives implemented #{right} " if right < 0
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left = :pc
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left = :pc
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end
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end
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if (right.is_a?(Numeric))
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if (right.is_a?(Numeric))
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@ -42,7 +45,17 @@ module Arm
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operand = op_with_rot
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operand = op_with_rot
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immediate = 1
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immediate = 1
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else
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else
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raise "cannot fit numeric literal argument in operand #{right.inspect}"
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#TODO this is copied from MoveInstruction, should rework
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unless @extra
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@extra = 1
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raise ::Register::LinkException.new("cannot fit numeric literal argument in operand #{right.inspect}")
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end
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# now we can do the actual breaking of instruction, by splitting the operand
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first = right & 0xFFFFFF00
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operand = calculate_u8_with_rr( first )
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raise "no fit for #{right}" unless operand
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immediate = 1
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@extra = ArmMachine.add( result , result , (right & 0xFF) )
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end
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end
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elsif (right.is_a?(Symbol) or right.is_a?(::Register::RegisterReference))
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elsif (right.is_a?(Symbol) or right.is_a?(::Register::RegisterReference))
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operand = reg_code(right) #integer means the register the integer is in (otherwise constant)
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operand = reg_code(right) #integer means the register the integer is in (otherwise constant)
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@ -62,12 +75,22 @@ module Arm
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val |= shift(instuction_class , 12+4+4 + 1+4+1)
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val |= shift(instuction_class , 12+4+4 + 1+4+1)
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val |= shift(cond_bit_code , 12+4+4 + 1+4+1+2)
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val |= shift(cond_bit_code , 12+4+4 + 1+4+1+2)
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io.write_uint32 val
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io.write_uint32 val
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# by now we have the extra add so assemble that
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if(@extra)
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@extra.assemble(io)
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#puts "Assemble extra at #{val.to_s(16)}"
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end
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end
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end
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def shift val , by
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def shift val , by
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raise "Not integer #{val}:#{val.class} #{inspect}" unless val.is_a? Fixnum
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raise "Not integer #{val}:#{val.class} #{inspect}" unless val.is_a? Fixnum
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val << by
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val << by
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end
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end
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def word_length
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@extra ? 8 : 4
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end
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def uses
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def uses
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ret = []
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ret = []
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ret << @left.register if @left and not @left.is_a? Constant
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ret << @left.register if @left and not @left.is_a? Constant
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@ -7,7 +7,7 @@ module Arm
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constant = code.constant
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constant = code.constant
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if constant.is_a?(Parfait::Object) or constant.is_a? Symbol
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if constant.is_a?(Parfait::Object) or constant.is_a? Symbol
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load = ArmMachine.add( code.register , :pc , constant )
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load = ArmMachine.add( code.register , constant )
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else
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else
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load = ArmMachine.mov( code.register , code.constant )
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load = ArmMachine.mov( code.register , code.constant )
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end
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end
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