fix the exit sequence
was returning wrong register (1, not 0) also saving the message for test, which changes order as the return value destroys the message
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@ -13,8 +13,8 @@ module Risc
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#show_main_ticks # get output of what is
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check_main_chain [LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
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RegToSlot, SlotToReg, SlotToReg, RegToSlot, SlotToReg,
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SlotToReg, SlotToReg, FunctionReturn, SlotToReg, SlotToReg,
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Branch, Transfer, Syscall, NilClass]
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SlotToReg, SlotToReg, FunctionReturn, Transfer, SlotToReg,
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Branch, SlotToReg, Syscall, NilClass]
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assert_equal 15 , get_return
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end
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@ -36,7 +36,7 @@ module Risc
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assert_equal Fixnum , link.class
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end
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def test_transfer
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transfer = main_ticks(17)
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transfer = main_ticks(14)
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assert_equal Transfer , transfer.class
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end
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def test_sys
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