diff --git a/lib/arm/attributed.rb b/lib/arm/attributed.rb
index 09cba099..5cea07d2 100644
--- a/lib/arm/attributed.rb
+++ b/lib/arm/attributed.rb
@@ -38,6 +38,7 @@ module Arm
 end
 
 require_relative "constants"
+require_relative "instructions/instruction"
 require_relative "instructions/call_instruction"
 require_relative "instructions/compare_instruction"
 require_relative "instructions/logic_instruction"
diff --git a/lib/arm/instructions/call_instruction.rb b/lib/arm/instructions/call_instruction.rb
index 307beaf9..67795a75 100644
--- a/lib/arm/instructions/call_instruction.rb
+++ b/lib/arm/instructions/call_instruction.rb
@@ -9,9 +9,7 @@ module Arm
   # swi (SoftWareInterrupt) or system call is how we call the kernel.
   # in Arm the register layout is different and so we have to place the syscall code into register 7
   # Riscs 0-6 hold the call values as for a normal c call
-  class CallInstruction < Risc::Branch
-    include Constants
-    include Attributed
+  class CallInstruction < Instruction
 
     def initialize(first, attributes)
       super(nil, nil)
diff --git a/lib/arm/instructions/compare_instruction.rb b/lib/arm/instructions/compare_instruction.rb
index 64686966..968514bf 100644
--- a/lib/arm/instructions/compare_instruction.rb
+++ b/lib/arm/instructions/compare_instruction.rb
@@ -1,7 +1,5 @@
 module Arm
-  class CompareInstruction < Risc::Instruction
-    include Constants
-    include Attributed
+  class CompareInstruction < Instruction
 
     def initialize(left , right , attributes)
       super(nil)
diff --git a/lib/arm/instructions/instruction.rb b/lib/arm/instructions/instruction.rb
new file mode 100644
index 00000000..6029c784
--- /dev/null
+++ b/lib/arm/instructions/instruction.rb
@@ -0,0 +1,35 @@
+require "util/list"
+module Arm
+  # Arm instruction base class
+  # Mostly linked list functionality that all instructions have
+  class Instruction
+    include Constants
+    include Attributed
+    include Util::List
+
+    def initialize( source , nekst = nil )
+      @source = source
+      @next = nekst
+      return unless source
+      raise "Source must be string or Instruction, not #{source.class}" unless source.is_a?(String) or source.is_a?(Mom::Instruction)
+    end
+    attr_reader :source
+
+    def total_byte_length
+      ret = 0
+      self.each{|ins| ret += ins.byte_length}
+      ret
+    end
+
+    def set_position( position )
+      Positioned.set_position(self,position)
+      position += byte_length
+      if self.next
+        self.next.set_position( position )
+      else
+        position
+      end
+    end
+
+  end
+end
diff --git a/lib/arm/instructions/logic_instruction.rb b/lib/arm/instructions/logic_instruction.rb
index 14f0d240..704106f1 100644
--- a/lib/arm/instructions/logic_instruction.rb
+++ b/lib/arm/instructions/logic_instruction.rb
@@ -1,7 +1,5 @@
 module Arm
-  class LogicInstruction < Risc::Instruction
-    include Constants
-    include Attributed
+  class LogicInstruction < Instruction
 
     #  result = left op right   #or constant loading
     #
@@ -62,7 +60,7 @@ module Arm
 
     # Arm can't load any large (over 1024) numbers, or larger with fancy shifting,
     # but then the lower bits must be 0's. Especially in constant loading random large numbers
-    # happen, and so they are split into two instructions. An exection is thrown, that triggers
+    # happen, and so they are split into two instructions. An exeption is thrown, that triggers
     # some position handling and an @extra add instruction generated.
     def handle_numeric(right)
       if (right.fits_u8?)
diff --git a/lib/arm/instructions/memory_instruction.rb b/lib/arm/instructions/memory_instruction.rb
index 71fc300a..090d6b89 100644
--- a/lib/arm/instructions/memory_instruction.rb
+++ b/lib/arm/instructions/memory_instruction.rb
@@ -2,9 +2,7 @@ module Arm
   # ADDRESSING MODE 2
   # Implemented: immediate offset with offset=0
 
-  class MemoryInstruction < Risc::Instruction
-    include Constants
-    include Attributed
+  class MemoryInstruction < Instruction
 
     def initialize result , left , right = nil , attributes = {}
       super(nil)
@@ -46,7 +44,7 @@ module Arm
       # but gnu as produces same output for auto_inc or not, so that seems broken
       # luckily auto_inc is not used and even if it clobbers unused reg in soml, but still
 
-      val = shift(val , 0 ) 
+      val = shift(val , 0 )
       val |= shift(reg_code(arg) ,  16)
       val |= shift(i ,              25)
       write_val(val, io)
diff --git a/lib/arm/instructions/move_instruction.rb b/lib/arm/instructions/move_instruction.rb
index d30bc545..241c1884 100644
--- a/lib/arm/instructions/move_instruction.rb
+++ b/lib/arm/instructions/move_instruction.rb
@@ -1,9 +1,7 @@
 module Arm
-  class MoveInstruction < Risc::Instruction
-    include Constants
-    include Attributed
+  class MoveInstruction < Instruction
 
-    def initialize to , from , options = {}
+    def initialize( to , from , options = {})
       super(nil)
       @attributes = options
       if( from.is_a?(Symbol) and Risc::RiscValue.look_like_reg(from) )
diff --git a/lib/arm/instructions/stack_instruction.rb b/lib/arm/instructions/stack_instruction.rb
index b4eb632c..491f65e1 100644
--- a/lib/arm/instructions/stack_instruction.rb
+++ b/lib/arm/instructions/stack_instruction.rb
@@ -1,9 +1,7 @@
 module Arm
   # ADDRESSING MODE 4
 
-  class StackInstruction < Risc::Instruction
-    include Constants
-    include Attributed
+  class StackInstruction < Instruction
 
     def initialize(first , attributes)
       super(nil)