allow reverse syntax for >> (ie <<)
slot >> reg makes sense, being a slot_to_reg but . . . consistently use of << (as meaning assignment , =) also makes sense allow both and let time tell which makes more sense
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@ -68,6 +68,8 @@ module Risc
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ins = Risc.load_constant("#{load.class} to #{self.type}" , load , self)
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when RiscValue
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ins = Risc.transfer("#{load.type} to #{self.type}" , load , self)
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when RValue
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load >> self
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else
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raise "not implemented"
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end
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