allow reverse syntax for >> (ie <<)

slot >> reg makes sense, being a slot_to_reg
but . . .
consistently use of << (as meaning assignment , =) also makes sense
allow both and let time tell which makes more sense
This commit is contained in:
Torsten Ruger
2018-04-06 21:05:26 +03:00
parent 41d573d571
commit c042dd9faa
3 changed files with 9 additions and 2 deletions

View File

@ -68,6 +68,8 @@ module Risc
ins = Risc.load_constant("#{load.class} to #{self.type}" , load , self)
when RiscValue
ins = Risc.transfer("#{load.type} to #{self.type}" , load , self)
when RValue
load >> self
else
raise "not implemented"
end