minor fixes
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@ -130,6 +130,10 @@ module Arm
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ArmMachine.beq( code.label.to_cpu(self) )
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end
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def translate_IsNotZero( code )
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ArmMachine.bne( code.label.to_cpu(self) )
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end
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def translate_IsOverflow( code )
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ArmMachine.bvs( code.label.to_cpu(self))
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end
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@ -45,7 +45,7 @@ module Risc
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end
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def source_mini
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return "(no source)" unless source
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return "(from: #{source[0..25]})" if source.is_a?(String)
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return "(from: #{source[0..35]})" if source.is_a?(String)
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"(from: #{source.class.name.split("::").last})"
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end
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end
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@ -79,6 +79,7 @@ module Risc
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end
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return if old === val
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reg = reg.symbol if reg.is_a? Risc::RiscValue
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val = Parfait.object_space.nil_object if( val == nil) #because that's what real code has
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@registers[reg] = val
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trigger(:register_changed, reg , old , val)
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end
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@ -93,7 +93,7 @@ module Risc
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# for computationally building code (ie writing assembler) these short cuts
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# help to instantiate risc instructions and add them immediately
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[:label, :reg_to_slot , :slot_to_reg , :load_constant, :load_data,
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:function_return , :function_call,
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:function_return , :function_call, :op ,
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:transfer , :reg_to_slot , :byte_to_reg , :reg_to_byte].each do |method|
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define_method("add_#{method}".to_sym) do |*args|
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add_code Risc.send( method , *args )
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