move message to stack_pointer

changing a bunch of register names
some of which get names now
This commit is contained in:
2020-03-22 11:29:56 +02:00
parent a93a3c8af5
commit be684c0c43
17 changed files with 78 additions and 68 deletions

View File

@ -16,16 +16,15 @@ module Risc
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, #15
FunctionCall, LoadConstant, SlotToReg, OperatorInstruction, IsZero, #20
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #25
RegToSlot, SlotToReg, LoadConstant, RegToSlot, SlotToReg, #30
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, #30
SlotToReg, DynamicJump, LoadConstant, SlotToReg, SlotToReg, #35
RegToSlot, LoadConstant, RegToSlot, Branch, SlotToReg, #40
SlotToReg, RegToSlot, SlotToReg, SlotToReg, SlotToReg, #45
FunctionReturn, SlotToReg, RegToSlot, Branch, SlotToReg, #50
SlotToReg, RegToSlot, SlotToReg, SlotToReg, SlotToReg, #55
FunctionReturn, SlotToReg, RegToSlot, Branch, SlotToReg, #60
SlotToReg, RegToSlot, SlotToReg, SlotToReg, SlotToReg, #65
FunctionReturn, Transfer, SlotToReg, SlotToReg, Syscall, #70
NilClass,] #75
SlotToReg, RegToSlot, SlotToReg, SlotToReg, FunctionReturn, #45
SlotToReg, RegToSlot, Branch, SlotToReg, SlotToReg, #50
RegToSlot, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, #55
RegToSlot, Branch, SlotToReg, SlotToReg, RegToSlot, #60
SlotToReg, SlotToReg, FunctionReturn, Transfer, SlotToReg, #65
SlotToReg, Transfer, Syscall, NilClass,] #70
assert_equal 10 , get_return
end
def base ; 32 ; end
@ -36,23 +35,21 @@ module Risc
assert_equal Parfait::Block , @interpreter.get_register(load_ins.register).class
end
def test_block_load
load_ins = main_ticks(base+1)
assert_load load_ins , Parfait::Integer , :r1
assert_equal 10 , @interpreter.get_register(load_ins.register).value
assert_load base+1 , Parfait::Integer , :r0
assert_equal 10 , @interpreter.get_register(risc(base+1).register).value
end
def test_block_slot1
assert_slot_to_reg main_ticks(base+2) ,:r0 , 6 , :r2
assert_slot_to_reg base+2 ,:r13 , 6 , :r1
end
def test_block_slot2
assert_slot_to_reg main_ticks(base+3) ,:r2 , 6 , :r2
assert_slot_to_reg base+3 ,:r1 , 6 , :r2
end
def test_block_reg
assert_reg_to_slot main_ticks(base+4) ,:r1 , :r2 , 16
assert_reg_to_slot base+4 ,:r0 , :r2 , 16
end
def test_ret_load
load_ins = main_ticks(base+5)
assert_load load_ins , Parfait::Integer , :r1
assert_equal 15 , @interpreter.get_register(load_ins.register).value
assert_load base+5 , Parfait::Integer , :r0
assert_equal 15 , @interpreter.get_register(risc(base+5).register).value
end
end
end