implement smaller than comparison
which is NOT an operator in the risc sense rather a minus and a check for sign (which _could be more efficient in arm, with conditional execution)
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@ -114,7 +114,7 @@ module Risc
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add_slot_to_reg(source , int_arg , at + 1, int_arg ) #1 for type
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return int_arg
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end
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# assumed Integer in given register is replaced by the fixnum that it is holding
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def reduce_int( source , register )
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add_slot_to_reg( source + "int -> fix" , register , Parfait::Integer.integer_index , register)
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