continue with #11

slots are the most tricky, especially testing
This commit is contained in:
Torsten Ruger 2018-08-19 13:06:00 +03:00
parent 047a36178f
commit b294208025
4 changed files with 43 additions and 32 deletions

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@ -40,32 +40,31 @@ module Mom
def to_risc(compiler)
#puts "RISC #{self}"
const = @right.to_register(compiler , original_source)
const_reg = @right.to_register(compiler , original_source)
left_slots = @left.slots
case @left.known_object
when Symbol
sym_to_risc(compiler , const)
sym_to_risc(compiler , const_reg)
when Parfait::CacheEntry
left = compiler.use_reg( :CacheEntry )
const << Risc.load_constant(original_source, @left.known_object , left)
const << Risc.reg_to_slot(original_source, const.register , left, left_slots.first)
compiler.add_code Risc.load_constant(original_source, @left.known_object , left)
compiler.add_code Risc.reg_to_slot(original_source, const.register , left, left_slots.first)
else
raise "We have left #{@left.known_object}"
end
compiler.reset_regs
return const
end
def sym_to_risc(compiler , const)
def sym_to_risc(compiler , const_reg)
left_slots = @left.slots.dup
raise "Not Message #{object}" unless @left.known_object == :message
left = Risc.message_reg
slot = left_slots.shift
while( !left_slots.empty? )
left = left.resolve_and_add( slot , const , compiler)
left = left.resolve_and_add( slot , compiler)
slot = left_slots.shift
end
const << Risc.reg_to_slot(original_source, const.register , left, slot)
compiler.add_code Risc.reg_to_slot(original_source, const_reg , left, slot)
end
end

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@ -5,34 +5,35 @@ module Mom
def setup
Parfait.boot!
@load = SlotLoad.new( [:message, :caller] , [:message,:type] )
load = SlotLoad.new( [:message, :caller] , [:message,:type] )
@compiler = Risc::FakeCompiler.new
@instruction = @load.to_risc(@compiler)
load.to_risc(@compiler)
@instructions = @compiler.instructions
end
def test_ins_class
assert_equal Risc::SlotToReg , @instruction.class
assert_equal Risc::SlotToReg , @instructions[0].class
end
def test_ins_next_class
assert_equal Risc::RegToSlot , @instruction.next.class
assert_equal Risc::RegToSlot , @instructions[1].class
end
def test_ins_arr
assert_equal :r0 , @instruction.array.symbol
assert_equal :r0 , @instructions[0].array.symbol
end
def test_ins_reg
assert_equal :r1 , @instruction.register.symbol
assert_equal :r1 , @instructions[0].register.symbol
end
def test_ins_index
assert_equal 0 , @instruction.index
assert_equal 0 , @instructions[0].index
end
def test_ins_next_reg
assert_equal :r1 , @instruction.next.register.symbol
assert_equal :r1 , @instructions[1].register.symbol
end
def test_ins_next_arr
assert_equal :r0 , @instruction.next.array.symbol
assert_equal :r0 , @instructions[1].array.symbol
end
def test_ins_next_index
assert_equal 6 , @instruction.next.index
assert_equal 6 , @instructions[1].index
end
end
end

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@ -5,47 +5,48 @@ module Mom
def setup
Parfait.boot!
@load = SlotLoad.new( [:message, :caller, :type] , [:message, :caller , :type] )
@compiler = Risc::FakeCompiler.new
@instruction = @load.to_risc(@compiler)
load = SlotLoad.new( [:message, :caller, :type] , [:message, :caller , :type] )
load.to_risc(@compiler)
@instructions = @compiler.instructions
end
def test_ins_next_class
assert_equal Risc::SlotToReg , @instruction.next(1).class
assert_equal Risc::SlotToReg , @instruction.next(2).class
assert_equal Risc::SlotToReg , @instructions[1].class
assert_equal Risc::SlotToReg , @instructions[2].class
end
def test_ins_next_next_class
assert_equal Risc::RegToSlot , @instruction.next(3).class
assert_equal Risc::RegToSlot , @instructions[3].class
end
def test_ins_next_reg
assert_equal :r1 , @instruction.next.register.symbol
assert_equal :r1 , @instructions[1].register.symbol
end
def test_ins_next_arr
assert_equal :r1 , @instruction.next.array.symbol
assert_equal :r1 , @instructions[1].array.symbol
end
def test_ins_next_index
assert_equal 0 , @instruction.next.index
assert_equal 0 , @instructions[1].index
end
def test_ins_next_2_reg
assert_equal :r1 , @instruction.next(2).register.symbol
assert_equal :r1 , @instructions[2].register.symbol
end
def test_ins_next_2_arr
assert_equal :r0 , @instruction.next(2).array.symbol
assert_equal :r0 , @instructions[2].array.symbol
end
def test_ins_next_2_index
assert_equal 6 , @instruction.next(2).index
assert_equal 6 , @instructions[2].index
end
def test_ins_next_3_reg
assert_equal :r1 , @instruction.next(3).register.symbol
assert_equal :r1 , @instructions[3].register.symbol
end
def test_ins_next_3_arr
assert_equal :r1 , @instruction.next(3).array.symbol
assert_equal :r1 , @instructions[3].array.symbol
end
def test_ins_next_3_index
assert_equal 0 , @instruction.next(3).index
assert_equal 0 , @instructions[3].index
end
end
end

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@ -1,5 +1,15 @@
module Risc
class FakeCompiler
attr_reader :instructions
def initialize
@instructions = []
end
def add_code(c)
@instructions << c
end
def current
@instructions.last
end
def slot_type(slot,type)
type.type_for(slot)
end