rename unit and sint to human readable forms
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@ -67,7 +67,7 @@ module Arm
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# signed 32-bit, condense to 24-bit
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# TODO add check that the value fits into 24 bits
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io << packed[0,3]
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io.write_uint8 op_bit_code | (COND_CODES[@attributes[:condition_code]] << 4)
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io.write_unsigned_int_8 op_bit_code | (COND_CODES[@attributes[:condition_code]] << 4)
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end
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def handle_swi(io)
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@ -75,7 +75,7 @@ module Arm
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raise "expected literal not #{arg} #{inspect}" unless (arg.is_a?(Numeric))
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packed = [arg].pack('L')[0,3]
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io << packed
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io.write_uint8 0b1111 | (COND_CODES[@attributes[:condition_code]] << 4)
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io.write_unsigned_int_8 0b1111 | (COND_CODES[@attributes[:condition_code]] << 4)
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end
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def to_s
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@ -43,7 +43,7 @@ module Arm
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val |= shift(immediate , 12 + 4 + 4 + 1 + 4)
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val |= instruction_code
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val |= condition_code
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io.write_uint32 val
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io.write_unsigned_int_32 val
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end
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def instuction_class
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@ -48,7 +48,7 @@ module Arm
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val |= shift(immediate , 12 + 4 + 4 + 1 + 4)
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val |= instruction_code
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val |= condition_code
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io.write_uint32 val
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io.write_unsigned_int_32 val
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assemble_extra(io)
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end
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@ -62,7 +62,7 @@ module Arm
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val |= shift(1, 24) #pre_post index , not used
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val |= instruction_code
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val |= condition_code
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io.write_uint32 val
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io.write_unsigned_int_32 val
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end
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def get_operand
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return @operand unless @right
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@ -56,7 +56,7 @@ module Arm
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val |= shift(immediate , 12 + 4 + 4 + 1 + 4)
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val |= instruction_code
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val |= condition_code
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io.write_uint32 val
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io.write_unsigned_int_32 val
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# by now we have the extra add so assemble that
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@extra.assemble(io) if(@extra) #puts "Assemble extra at #{val.to_s(16)}"
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end
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@ -32,7 +32,7 @@ module Arm
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val = val | (pre_post_index << 16 + 4 + 1 + 1 + 1 + 1)#24
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val = val | instruction_code
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val = val | (cond << 16 + 4 + 1 + 1 + 1 + 1 + 2 + 2)
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io.write_uint32 val
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io.write_unsigned_int_32 val
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end
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def cond
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