another +1 bug

This commit is contained in:
Torsten Ruger
2018-05-15 16:25:55 +03:00
parent e237bc625a
commit ab4bc370ed
6 changed files with 20 additions and 6 deletions

View File

@ -50,7 +50,7 @@ module Risc
assert_equal RegToSlot , produced.next(base+3).class
assert_equal :r1 , produced.next(base+3).register.symbol
assert_equal :r3 , produced.next(base+3).array.symbol
assert_equal 2 , produced.next(base+3).index , "first arg must have index 1"
assert_equal 1 , produced.next(base+3).index , "first arg must have index 1"
end
def test_load_label
produced = produce_body