rename register to risc

seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 09:02:29 +02:00
parent da5823a1a0
commit aa79e41d1c
127 changed files with 348 additions and 346 deletions
--- a/test/bench/vm/helper.rb
+++ b/test/bench/vm/helper.rb
@ -8,7 +8,7 @@ module BenchTests

  def setup
    @stdout =  ""
-    @machine = Register.machine.boot
+    @machine = Risc.machine.boot
    # Vm::Compiler.load_parfait
    # most interesting parts saved as interger/word .soml in this dir
  end