rename register to risc

seems to fit the layer much better as we really have a very reduced
instruction set
This commit is contained in:
Torsten Ruger
2017-01-19 09:02:29 +02:00
parent da5823a1a0
commit aa79e41d1c
127 changed files with 348 additions and 346 deletions

View File

@ -11,7 +11,7 @@ module ParfaitTests
def setup
@stdout = ""
@machine = Register.machine.boot
@machine = Risc.machine.boot
Vm::Compiler.load_parfait
end