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rename register to risc

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seems to fit the layer much better as we really have a very reduced
instruction set
This commit is contained in:
Torsten Ruger
2017-01-19 09:02:29 +02:00
parent da5823a1a0
commit aa79e41d1c
127 changed files with 348 additions and 346 deletions
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10
lib/vm/method_compiler.rb
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@ -131,7 +131,7 @@ module Vm
def init_method
source = "_init_method"
name = "#{method.for_type.name}.#{method.name}"
@current = @method.set_instructions( Register.label(source, name))
@current = @method.set_instructions( Risc.label(source, name))
# add the type of the locals to the existing NamedList instance
locals_reg = use_reg(:Type , method.locals )
@ -143,7 +143,7 @@ module Vm
enter = @current # this is where method body goes
add_label( source, "return #{name}")
#load the return address into pc, affecting return. (other cpus have commands for this, but not arm)
add_function_return( source , Register.message_reg , Register.resolve_to_index(:message , :return_address) )
add_function_return( source , Risc.message_reg , Risc.resolve_to_index(:message , :return_address) )
@current = enter
self
end
@ -156,7 +156,7 @@ module Vm
# add an instruction after the current (insertion point)
# the added instruction will become the new insertion point
def add_code instruction
raise instruction.to_s unless instruction.is_a?(Register::Instruction)
raise instruction.to_s unless instruction.is_a?(Risc::Instruction)
raise instruction.to_s if( instruction.class.name.split("::").first == "Arm")
@current.insert(instruction) #insert after current
@current = instruction
@ -166,7 +166,7 @@ module Vm
[:label, :reg_to_slot , :slot_to_reg , :load_constant, :function_return ,
:transfer , :reg_to_slot , :byte_to_reg , :reg_to_byte].each do |method|
define_method("add_#{method}".to_sym) do |*args|
add_code Register.send( method , *args )
add_code Risc.send( method , *args )
end
end
@ -174,7 +174,7 @@ module Vm
def use_reg( type , value = nil )
raise "Not type #{type.inspect}" unless type.is_a?(Symbol) or type.is_a?(Parfait::Type)
if @regs.empty?
reg = Register.tmp_reg(type , value)
reg = Risc.tmp_reg(type , value)
else
reg = @regs.last.next_reg_use(type , value)
end

2
lib/vm/method_compiler/assignment.rb
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@ -42,7 +42,7 @@ module Vm
def assignment_value(statement)
reset_regs # statements reset registers, ie have all at their disposal
value = process(statement.value)
raise "Not register #{v}" unless value.is_a?(Register::RegisterValue)
raise "Not register #{v}" unless value.is_a?(Risc::RiscValue)
value
end
# ensure the name given is not space and raise exception otherwise

4
lib/vm/method_compiler/basic_values.rb
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@ -5,7 +5,7 @@ module Vm
# Constant expressions can by definition be evaluated at compile time.
# But that does not solve their storage, ie they need to be accessible at runtime from _somewhere_
# So expressions move the data into a Register.
# So expressions move the data into a Risc.
# All expressions return registers
# But in the future (in the one that holds great things) we optimize those unneccesay moves away
@ -38,7 +38,7 @@ module Vm
def on_StringExpression expression
value = Parfait.new_word expression.value.to_sym
reg = use_reg :Word
Register.machine.constants << value
Risc.machine.constants << value
add_load_constant( expression, value , reg )
return reg
end

6
lib/vm/method_compiler/call_site.rb
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@ -19,7 +19,7 @@ module Vm
set_arguments(method , statement.arguments)
ret = use_reg( :Object ) #FIXME real return type
Register.issue_call( self , method )
Risc.issue_call( self , method )
# the effect of the method is that the NewMessage Return slot will be filled, return it
# but move it into a register too
@ -30,7 +30,7 @@ module Vm
private
def load_new_message(statement)
new_message = Register.resolve_to_register(:new_message)
new_message = Risc.resolve_to_register(:new_message)
add_slot_to_reg(statement, :message , :next_message , new_message )
new_message
end
@ -87,7 +87,7 @@ module Vm
reset_regs
i = i + 1 # disregarding type field
val = process( arg) # processing should return the register with the value
raise "Not register #{val}" unless val.is_a?(Register::RegisterValue)
raise "Not register #{val}" unless val.is_a?(Risc::RiscValue)
#FIXME definately needs some tests
raise "TypeMismatch calling with #{val.type} , instead of #{arg_type.type_at(i)}" if val.type != arg_type.type_at(i)
list_reg = use_reg(:NamedList , arguments )

8
lib/vm/method_compiler/if_statement.rb
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@ -20,8 +20,8 @@ module Vm
def compile_if_condition( statement )
reset_regs
process(statement.condition)
branch_class = Object.const_get "Register::Is#{statement.branch_type.capitalize}"
true_block = Register.label(statement, "if_true")
branch_class = Object.const_get "Risc::Is#{statement.branch_type.capitalize}"
true_block = Risc.label(statement, "if_true")
add_code branch_class.new( statement.condition , true_block )
return true_block
end
@ -33,8 +33,8 @@ module Vm
def compile_if_false( statement )
reset_regs
process(statement.if_false) if statement.if_false.statements
merge = Register.label(statement , "if_merge")
add_code Register::Branch.new(statement.if_false, merge )
merge = Risc.label(statement , "if_merge")
add_code Risc::Branch.new(statement.if_false, merge )
merge
end
end

2
lib/vm/method_compiler/name_expression.rb
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@ -51,7 +51,7 @@ module Vm
def load_special_message(statement)
reg = use_reg :Message
add_transfer( "#{statement} load message", Register.message_reg , reg )
add_transfer( "#{statement} load message", Risc.message_reg , reg )
return reg
end
end #module

6
lib/vm/method_compiler/operator_expression.rb
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@ -6,9 +6,9 @@ module Vm
# left and right must be expressions. Expressions return a register when compiled
left_reg = process(statement.left_expression)
right_reg = process(statement.right_expression)
raise "Not register #{left_reg}" unless left_reg.is_a?(Register::RegisterValue)
raise "Not register #{right_reg}" unless right_reg.is_a?(Register::RegisterValue)
add_code Register::OperatorInstruction.new(statement,statement.operator,left_reg,right_reg)
raise "Not register #{left_reg}" unless left_reg.is_a?(Risc::RiscValue)
raise "Not register #{right_reg}" unless right_reg.is_a?(Risc::RiscValue)
add_code Risc::OperatorInstruction.new(statement,statement.operator,left_reg,right_reg)
return left_reg # though this has wrong value attached
end
end

8
lib/vm/method_compiler/while_statement.rb
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@ -13,7 +13,7 @@ module Vm
compile_while_condition( statement )
branch_class = Object.const_get "Register::Is#{statement.branch_type.capitalize}"
branch_class = Object.const_get "Risc::Is#{statement.branch_type.capitalize}"
# this is where the while ends and both branches meet
add_code branch_class.new( statement.condition , start )
@ -22,13 +22,13 @@ module Vm
private
def compile_while_preamble( statement )
condition_label = Register.label(statement.condition , "condition_label")
condition_label = Risc.label(statement.condition , "condition_label")
# unconditionally branch to the condition upon entering the loop
add_code Register::Branch.new(statement.condition , condition_label)
add_code Risc::Branch.new(statement.condition , condition_label)
condition_label
end
def compile_while_body( statement )
start = Register.label(statement , "while_start" )
start = Risc.label(statement , "while_start" )
add_code start
reset_regs
process(statement.statements)