rename register to risc

seems to fit the layer much better as we really have a very reduced
instruction set
This commit is contained in:
Torsten Ruger
2017-01-19 09:02:29 +02:00
parent da5823a1a0
commit aa79e41d1c
127 changed files with 348 additions and 346 deletions

View File

@ -0,0 +1,21 @@
module Risc
# RegToByte moves a byte into memory from a register.
# indexes are 1 based !
class RegToByte < Setter
end
# Produce a RegToByte instruction.
# from and to are translated (from symbol to register if neccessary)
# but index is left as is.
def self.reg_to_byte( source , from , to , index)
from = resolve_to_register from
index = resolve_to_index( to , index)
to = resolve_to_register to
RegToByte.new( source, from , to , index)
end
end