rename register to risc

seems to fit the layer much better as we really have a very reduced
instruction set
This commit is contained in:
Torsten Ruger
2017-01-19 09:02:29 +02:00
parent da5823a1a0
commit aa79e41d1c
127 changed files with 348 additions and 346 deletions

View File

@ -0,0 +1,21 @@
module Risc
class OperatorInstruction < Instruction
def initialize source , operator , left , right
super(source)
@operator = operator
@left = left
@right = right
end
attr_reader :operator, :left , :right
def to_s
"OperatorInstruction: #{left} #{operator} #{right}"
end
end
def self.op source , operator , left , right
OperatorInstruction.new source , operator , left , right
end
end