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rename register to risc

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seems to fit the layer much better as we really have a very reduced
instruction set
This commit is contained in:
Torsten Ruger
2017-01-19 09:02:29 +02:00
parent da5823a1a0
commit aa79e41d1c
127 changed files with 348 additions and 346 deletions
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6
lib/arm/instructions/call_instruction.rb
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@ -8,8 +8,8 @@ module Arm
# swi (SoftWareInterrupt) or system call is how we call the kernel.
# in Arm the register layout is different and so we have to place the syscall code into register 7
# Registers 0-6 hold the call values as for a normal c call
class CallInstruction < Register::Branch
# Riscs 0-6 hold the call values as for a normal c call
class CallInstruction < Risc::Branch
include Constants
include Attributed
@ -44,7 +44,7 @@ module Arm
def handle_call(io)
case @first
when Register::Label
when Risc::Label
# relative addressing for jumps/calls
# but because of the arm "theoretical" 3- stage pipeline,
# we have to subtract 2 words (fetch/decode)