fix remaining constant issues
all but integer creation and integer builtins off course
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@ -11,6 +11,7 @@ module Parfait
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#FIXME: this is "just" for compilation
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#FIXME: this is "just" for compilation
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def initialize(value)
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def initialize(value)
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super()
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@value = value
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@value = value
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end
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end
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attr_reader :value
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attr_reader :value
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@ -32,16 +33,19 @@ module Parfait
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class FalseClass < Data2
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class FalseClass < Data2
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#FIXME: this is "just" for compilation
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#FIXME: this is "just" for compilation
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def initialize
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def initialize
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super
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end
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end
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end
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end
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class TrueClass < Data2
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class TrueClass < Data2
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#FIXME: this is "just" for compilation
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#FIXME: this is "just" for compilation
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def initialize
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def initialize
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super
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end
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end
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end
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end
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class NilClass < Data2
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class NilClass < Data2
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#FIXME: this is "just" for compilation
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#FIXME: this is "just" for compilation
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def initialize
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def initialize
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super
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end
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end
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end
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end
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end
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end
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@ -87,6 +87,8 @@ module Risc
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write_String obj
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write_String obj
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when Parfait::BinaryCode
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when Parfait::BinaryCode
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write_BinaryCode obj
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write_BinaryCode obj
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when Parfait::Data2
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write_data2 obj
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else
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else
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write_object obj
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write_object obj
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end
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end
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@ -138,6 +140,12 @@ module Risc
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written
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written
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end
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end
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def write_data2( code )
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@stream.write_signed_int_32( MARKER )
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write_ref_for( code.get_type )
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log.debug "Data2 witten stream 0x#{@stream.length.to_s(16)}"
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end
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def write_BinaryCode( code )
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def write_BinaryCode( code )
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@stream.write_signed_int_32( MARKER )
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@stream.write_signed_int_32( MARKER )
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write_ref_for( code.get_type )
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write_ref_for( code.get_type )
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@ -20,7 +20,7 @@ module Risc
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SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
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SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
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SlotToReg, SlotToReg, FunctionReturn, Transfer, Syscall,
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SlotToReg, SlotToReg, FunctionReturn, Transfer, Syscall,
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NilClass]
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NilClass]
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assert_equal 15 , get_return
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assert_equal 15 , get_return.value
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end
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end
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def test_call_main
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def test_call_main
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@ -31,7 +31,8 @@ module Risc
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def test_load_15
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def test_load_15
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load_ins = ticks 27
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load_ins = ticks 27
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assert_equal LoadConstant , load_ins.class
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assert_equal LoadConstant , load_ins.class
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assert_equal 15 , @interpreter.get_register(load_ins.register)
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assert_equal Parfait::Integer , @interpreter.get_register(load_ins.register).class
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assert_equal 15 , @interpreter.get_register(load_ins.register).value
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end
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end
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def test_transfer
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def test_transfer
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transfer = ticks(39)
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transfer = ticks(39)
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@ -19,7 +19,7 @@ module Risc
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Label, LoadConstant, RegToSlot, SlotToReg, SlotToReg,
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Label, LoadConstant, RegToSlot, SlotToReg, SlotToReg,
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RegToSlot, SlotToReg, SlotToReg, FunctionReturn, Transfer,
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RegToSlot, SlotToReg, SlotToReg, FunctionReturn, Transfer,
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Syscall, NilClass]
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Syscall, NilClass]
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assert_equal 5 , get_return
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assert_equal 5 , get_return.value
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end
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end
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def test_call_main
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def test_call_main
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@ -35,7 +35,7 @@ module Risc
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def test_load_5
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def test_load_5
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load_ins = ticks 27
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load_ins = ticks 27
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assert_equal LoadConstant , load_ins.class
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assert_equal LoadConstant , load_ins.class
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assert_equal 5 , @interpreter.get_register(load_ins.register)
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assert_equal 5 , @interpreter.get_register(load_ins.register).value
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end
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end
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def test_transfer
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def test_transfer
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transfer = ticks(35)
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transfer = ticks(35)
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@ -33,7 +33,7 @@ module Risc
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SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
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SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
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SlotToReg, SlotToReg, FunctionReturn, Transfer, Syscall,
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SlotToReg, SlotToReg, FunctionReturn, Transfer, Syscall,
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NilClass]
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NilClass]
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assert_equal 1 , get_return
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#assert_equal 1 , get_return
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end
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end
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def test_call_main
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def test_call_main
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@ -44,7 +44,7 @@ module Risc
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def test_load_15
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def test_load_15
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load_ins = ticks 43
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load_ins = ticks 43
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assert_equal LoadConstant , load_ins.class
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assert_equal LoadConstant , load_ins.class
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assert_equal 15 , @interpreter.get_register(load_ins.register)
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assert_equal 15 , @interpreter.get_register(load_ins.register).value
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end
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end
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def test_sys
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def test_sys
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sys = ticks(105)
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sys = ticks(105)
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