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update to use parfait not virtual

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more ripples
reverting to integers (not virtual::integer)
This commit is contained in:
Torsten Ruger
2015-05-29 12:33:40 +03:00
parent c28430698c
commit a46b2d5c56
7 changed files with 49 additions and 66 deletions
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30
lib/arm/instructions/logic_instruction.rb
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@ -2,21 +2,21 @@ module Arm
class LogicInstruction < Instruction
include Arm::Constants
# result = left op right
#
#
# Logic instruction are your basic operator implementation. But unlike the (normal) code we write
# these Instructions must have "place" to write their results. Ie when you write 4 + 5 in ruby
# the result is sort of up in the air, but with Instructions the result must be assigned
# the result is sort of up in the air, but with Instructions the result must be assigned
def initialize(result , left , right , attributes = {})
super(attributes)
@result = result
@left = left
@right = right.is_a?(Fixnum) ? Virtual::IntegerConstant.new(right) : right
@right = right
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@operand = 0
raise "Left arg must be given #{inspect}" unless @left
@immediate = 0
@immediate = 0
end
attr_accessor :result , :left , :right
@ -27,17 +27,13 @@ module Arm
immediate = @immediate
right = @right
if @left.is_a?(Virtual::ObjectConstant)
if @left.is_a?(Parfait::Object)
# do pc relative addressing with the difference to the instuction
# 8 is for the funny pipeline adjustment (ie pointing to fetch and not execute)
right = @left.position - self.position - 8
right = @left.position - self.position - 8
left = :pc
end
# automatic wrapping, for machine internal code and testing
if( right.is_a? Fixnum )
right = Virtual::IntegerConstant.new( right )
end
if (right.is_a?(Virtual::IntegerConstant))
if (right.is_a?(Numeric))
if (right.fits_u8?)
# no shifting needed
operand = right.integer
@ -58,12 +54,12 @@ module Arm
instuction_class = 0b00 # OPC_DATA_PROCESSING
val = shift(operand , 0)
val |= shift(op , 0) # any barral action, is already shifted
val |= shift(reg_code(@result) , 12)
val |= shift(reg_code(left) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(reg_code(@result) , 12)
val |= shift(reg_code(left) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 +1)
val |= shift(immediate , 12+4+4 +1+4)
val |= shift(instuction_class , 12+4+4 +1+4+1)
val |= shift(immediate , 12+4+4 +1+4)
val |= shift(instuction_class , 12+4+4 +1+4+1)
val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
io.write_uint32 val
end
@ -71,7 +67,7 @@ module Arm
raise "Not integer #{val}:#{val.class} #{inspect}" unless val.is_a? Fixnum
val << by
end
def uses
ret = []
ret << @left.register if @left and not @left.is_a? Constant