update to use parfait not virtual
more ripples reverting to integers (not virtual::integer)
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@ -1,19 +1,19 @@
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module Arm
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class CompareInstruction < Instruction
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include Arm::Constants
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def initialize(left , right , attributes)
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super(attributes)
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@left = left
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@right = right.is_a?(Fixnum) ? IntegerConstant.new(right) : right
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@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
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@operand = 0
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@immediate = 0
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@immediate = 0
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@attributes[:update_status] = 1
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@rn = left
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@rd = :r0
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end
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def assemble(io)
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# don't overwrite instance variables, to make assembly repeatable
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rn = @rn
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@ -21,16 +21,16 @@ module Arm
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immediate = @immediate
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arg = @right
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if arg.is_a?(Virtual::ObjectConstant)
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if arg.is_a?(Parfait::Object)
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# do pc relative addressing with the difference to the instuction
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# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
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arg = Virtual::IntegerConstant.new( arg.position - self.position - 8 )
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arg = arg.position - self.position - 8
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rn = :pc
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end
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if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
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if( arg.is_a? Symbol )
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arg = Register::RegisterReference.new( arg )
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end
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if (arg.is_a?(Virtual::IntegerConstant))
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if (arg.is_a?(Numeric))
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if (arg.fits_u8?)
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# no shifting needed
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operand = arg.integer
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@ -54,7 +54,7 @@ module Arm
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# ror #0 == rrx
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raise "cannot rotate by zero #{arg} #{inspect}"
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end
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arg1 = arg.value
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if (arg1.is_a?(Virtual::IntegerConstant))
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if (arg1.value >= 32)
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@ -72,16 +72,16 @@ module Arm
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raise "invalid operand argument #{arg.inspect} , #{inspect}"
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end
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instuction_class = 0b00 # OPC_DATA_PROCESSING
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val = (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterReference)) ? reg_code(operand) : operand
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val = (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterReference)) ? reg_code(operand) : operand
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val = 0 if val == nil
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val = shift(val , 0)
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raise inspect unless reg_code(@rd)
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val |= shift(reg_code(@rd) , 12)
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val |= shift(reg_code(rn) , 12+4)
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val |= shift(@attributes[:update_status] , 12+4+4)#20
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val |= shift(reg_code(@rd) , 12)
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val |= shift(reg_code(rn) , 12+4)
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val |= shift(@attributes[:update_status] , 12+4+4)#20
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val |= shift(op_bit_code , 12+4+4 +1)
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val |= shift(immediate , 12+4+4 +1+4)
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val |= shift(instuction_class , 12+4+4 +1+4+1)
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val |= shift(immediate , 12+4+4 +1+4)
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val |= shift(instuction_class , 12+4+4 +1+4+1)
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val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
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io.write_uint32 val
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end
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