From a2e7d7c469ef09c8a18cc377c9a0b99592b6b1bb Mon Sep 17 00:00:00 2001 From: Torsten Ruger Date: Wed, 23 May 2018 18:05:22 +0300 Subject: [PATCH] give interpreter a clock and pc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit where the pc, like in cpu’s is the memory position. That is what the interpreter works on. But for humans, the clock is a simpler way to count where the program is at, no. of instructions executed --- lib/risc/instruction.rb | 2 +- lib/risc/interpreter.rb | 17 +++++++++-------- test/risc/test_interpreter.rb | 30 ++++++++++++++++++++++++------ 3 files changed, 34 insertions(+), 15 deletions(-) diff --git a/lib/risc/instruction.rb b/lib/risc/instruction.rb index 40d5aa05..0e17e941 100644 --- a/lib/risc/instruction.rb +++ b/lib/risc/instruction.rb @@ -46,7 +46,7 @@ module Risc end def source_mini return "(no source)" unless source - return "(from: #{source[0..35]})" if source.is_a?(String) + return "(from: #{source[0..50]})" if source.is_a?(String) "(from: #{source.class.name.split("::").last})" end end diff --git a/lib/risc/interpreter.rb b/lib/risc/interpreter.rb index 6a0b08ce..b021a6fe 100644 --- a/lib/risc/interpreter.rb +++ b/lib/risc/interpreter.rb @@ -14,15 +14,15 @@ module Risc # fire events for changed pc and register contents include Util::Eventable include Util::Logging - log_level :debug + log_level :info - attr_reader :instruction , :clock # current instruction or pc + attr_reader :instruction , :clock , :pc # current instruction and pc attr_reader :registers # the registers, 16 (a hash, sym -> contents) attr_reader :stdout, :state , :flags # somewhat like the lags on a cpu, hash sym => bool (zero .. . ) #start in state :stopped and set registers to unknown def initialize() - @stdout , @clock , @state = "", 0 , :stopped + @stdout , @clock , @pc , @state = "", 0 , 0 , :stopped @registers = {} @flags = { :zero => false , :plus => false , :minus => false , :overflow => false } @@ -53,8 +53,9 @@ module Risc return set_pc(position.at + 12) end raise "not instruction position #{position}-#{position.class}-#{position.object.class}" unless position.is_a?(Position::InstructionPosition) - set_instruction( position.instruction) - @clock = position.at + set_instruction( position.instruction ) + @clock += 1 + @pc = position.at end def set_instruction( instruction ) @@ -96,12 +97,12 @@ module Risc return @clock end name = @instruction.class.name.split("::").last - log.debug "#{@clock.to_s}: #{@instruction.to_s}" + log.debug "#{@pc.to_s}:#{@clock.to_s(16)}: #{@instruction.to_s}" fetch = send "execute_#{name}" log.debug register_dump if fetch - clock = @clock + @instruction.byte_length - set_pc(clock) + pc = @pc + @instruction.byte_length + set_pc(pc) else log.debug "No Fetch" end diff --git a/test/risc/test_interpreter.rb b/test/risc/test_interpreter.rb index 1bb86709..8782fcac 100644 --- a/test/risc/test_interpreter.rb +++ b/test/risc/test_interpreter.rb @@ -32,7 +32,7 @@ module Risc end def test_pos @interpreter.start_machine - assert_equal 0 , @interpreter.clock + assert_equal 1 , @interpreter.clock end end class TestInterpreterTicks < MiniTest::Test @@ -43,12 +43,30 @@ module Risc @interpreter = Interpreter.new @interpreter.start_machine end - def test_tick - assert_equal 19484 , @interpreter.tick + def test_tick1 + assert_equal 2 , @interpreter.tick end - def test_tick - assert_equal 19484 , @interpreter.tick - assert_equal 19488 , @interpreter.tick + def test_clock1 + @interpreter.tick + assert_equal 2 , @interpreter.clock + end + def test_pc1 + @interpreter.tick + assert_equal 19484 , @interpreter.pc + end + def test_tick2 + @interpreter.tick + assert_equal 3 , @interpreter.tick + end + def test_clock2 + @interpreter.tick + @interpreter.tick + assert_equal 3 , @interpreter.clock + end + def test_pc2 + @interpreter.tick + @interpreter.tick + assert_equal 19488 , @interpreter.pc end end end