fix mod and tests

This commit is contained in:
Torsten 2020-03-15 15:15:07 +02:00
parent 3a983b4fc8
commit 9f609bdb06
7 changed files with 61 additions and 102 deletions

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@ -9,7 +9,7 @@ module SlotMachine
integer_self = message[:receiver].reduce_int(false) integer_self = message[:receiver].reduce_int(false)
load_object( 2 , integer_1) load_object( 2 , integer_1)
result = integer_self.op :>> , integer_1 result = integer_self.op :>> , integer_1
integer_tmp[Parfait::Integer.integer_index] << result.result integer_tmp[Parfait::Integer.integer_index] << result
message[:return_value] << integer_tmp message[:return_value] << integer_tmp
end end
return compiler return compiler

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@ -16,56 +16,41 @@ module Risc
check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #5 check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #5
RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, #10 RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, #10
SlotToReg, RegToSlot, SlotToReg, FunctionCall, LoadConstant, #15 SlotToReg, RegToSlot, SlotToReg, FunctionCall, LoadConstant, #15
SlotToReg, LoadConstant, OperatorInstruction, IsNotZero, SlotToReg, #20 LoadConstant, SlotToReg, OperatorInstruction, IsNotZero, SlotToReg, #20
RegToSlot, SlotToReg, SlotToReg, SlotToReg, SlotToReg, #25 RegToSlot, SlotToReg, SlotToReg, SlotToReg, SlotToReg, #25
OperatorInstruction, RegToSlot, RegToSlot, SlotToReg, RegToSlot, #30 OperatorInstruction, RegToSlot, RegToSlot, SlotToReg, RegToSlot, #30
Branch, Branch, SlotToReg, SlotToReg, RegToSlot, #35 Branch, SlotToReg, SlotToReg, RegToSlot, SlotToReg, #35
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, #40 SlotToReg, FunctionReturn, SlotToReg, RegToSlot, Branch, #40
RegToSlot, Branch, SlotToReg, SlotToReg, RegToSlot, #45 SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #45
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer, #50 FunctionReturn, Transfer, SlotToReg, SlotToReg, Transfer, #50
SlotToReg, SlotToReg, Syscall, NilClass,] #55 Syscall, NilClass,] #55
assert_equal 10 , get_return assert_equal 10 , get_return
end end
def base_ticks(num)
main_ticks(14 + num)
end
def test_base
assert_equal FunctionCall , main_ticks( 14 ).class
end
def test_load_factory def test_load_factory
lod = base_ticks( 1 ) assert_load( 15 , Parfait::Factory , "id_factory_")
assert_load( lod , Parfait::Factory , :r2) assert_equal :next_integer , @instruction.constant.attribute_name
assert_equal :next_integer , lod.constant.attribute_name
end
def test_slot_receiver #load next_object from factory
sl = base_ticks( 2 )
assert_slot_to_reg( sl , :r2 , 2 , :r1)
end end
def test_load_nil def test_load_nil
lod = base_ticks( 3 ) assert_load( 16 , Parfait::NilClass , "id_nilclass_")
assert_load( lod , Parfait::NilClass , :r3) end
def test_slot_receiver #load next_object from factory
assert_slot_to_reg( 17 , "id_factory_" , 2 , "id_factory_.next_object")
end end
def test_nil_check def test_nil_check
op = base_ticks(4) assert_operator 18 , :- , "id_nilclass_" , "id_factory_.next_object" , "op_-_"
assert_equal OperatorInstruction , op.class value = @interpreter.get_register(@instruction.result)
assert_equal :- , op.operator assert_equal ::Integer , value.class
assert_equal :r3 , op.left.symbol assert 0 != value
assert_equal :r1 , op.right.symbol
assert_equal ::Integer , @interpreter.get_register(:r3).class
assert 0 != @interpreter.get_register(:r3)
end end
def test_branch def test_branch
br = base_ticks( 5 ) assert_not_zero 19 , "cont_label"
assert_equal IsNotZero , br.class
assert br.label.name.start_with?("cont_label")
end end
def test_load_next_int def test_load_next_int
sl = base_ticks( 6 ) assert_slot_to_reg( 20 , "id_factory_.next_object" , 1 , "id_factory_.next_object.next_integer")
assert_slot_to_reg( sl , :r1 , 1 , :r4)
end end
def test_move_next_back_to_factory def test_move_next_back_to_factory
int = base_ticks( 7 ) assert_reg_to_slot( 21 , "id_factory_.next_object.next_integer" , "id_factory_" , 2)
assert_reg_to_slot( int , :r4 , :r2 , 2)
end end
end end
end end

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@ -11,23 +11,23 @@ module Risc
end end
def test_chain def test_chain
#show_main_ticks # get output of what is # show_main_ticks # get output of what is
check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #5 check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #5
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, #10 RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, #10
FunctionCall, LoadConstant, SlotToReg, LoadConstant, OperatorInstruction, #15 FunctionCall, LoadConstant, LoadConstant, SlotToReg, OperatorInstruction, #15
IsNotZero, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #20 IsNotZero, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #20
Transfer, Transfer, LoadData, OperatorInstruction, LoadData, #25 Transfer, Transfer, LoadData, OperatorInstruction, LoadData, #25
OperatorInstruction, OperatorInstruction, Branch, LoadData, Transfer, #30 OperatorInstruction, OperatorInstruction, LoadData, Branch, Transfer, #30
OperatorInstruction, OperatorInstruction, LoadData, Transfer, OperatorInstruction, #35 OperatorInstruction, OperatorInstruction, LoadData, Transfer, OperatorInstruction, #35
OperatorInstruction, LoadData, Transfer, OperatorInstruction, OperatorInstruction, #40 OperatorInstruction, LoadData, Transfer, OperatorInstruction, OperatorInstruction, #40
LoadData, OperatorInstruction, LoadData, Transfer, OperatorInstruction, #45 LoadData, OperatorInstruction, LoadData, Transfer, OperatorInstruction, #45
OperatorInstruction, Transfer, LoadData, OperatorInstruction, LoadData, #50 OperatorInstruction, Transfer, LoadData, OperatorInstruction, LoadData, #50
OperatorInstruction, OperatorInstruction, RegToSlot, RegToSlot, SlotToReg, #55 OperatorInstruction, OperatorInstruction, RegToSlot, RegToSlot, SlotToReg, #55
RegToSlot, Branch, SlotToReg, SlotToReg, RegToSlot, #60 RegToSlot, Branch, SlotToReg, Branch, SlotToReg, #60
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, #65 RegToSlot, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, #65
RegToSlot, Branch, SlotToReg, SlotToReg, RegToSlot, #70 RegToSlot, Branch, SlotToReg, SlotToReg, RegToSlot, #70
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer, #75 SlotToReg, SlotToReg, FunctionReturn, Transfer, SlotToReg, #75
SlotToReg, SlotToReg, Syscall, NilClass,] #80 SlotToReg, Transfer, Syscall, NilClass,] #80
assert_equal 2 , get_return assert_equal 2 , get_return
end end
@ -37,10 +37,10 @@ module Risc
assert_equal 25 , @interpreter.get_register(load_ins.register).value assert_equal 25 , @interpreter.get_register(load_ins.register).value
end end
def test_return_class def test_return_class
ret = main_ticks(74) ret = risc(73)
assert_equal FunctionReturn , ret.class assert_equal FunctionReturn , ret.class
link = @interpreter.get_register( ret.register ) link = @interpreter.get_register( ret.register )
assert_equal ::Integer , link.class assert_equal Parfait::ReturnAddress , link.class
end end
end end
end end

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@ -15,30 +15,27 @@ module Risc
check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #5 check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #5
RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, #10 RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, #10
SlotToReg, RegToSlot, SlotToReg, FunctionCall, LoadConstant, #15 SlotToReg, RegToSlot, SlotToReg, FunctionCall, LoadConstant, #15
SlotToReg, LoadConstant, OperatorInstruction, IsNotZero, SlotToReg, #20 LoadConstant, SlotToReg, OperatorInstruction, IsNotZero, SlotToReg, #20
RegToSlot, SlotToReg, SlotToReg, SlotToReg, SlotToReg, #25 RegToSlot, SlotToReg, SlotToReg, SlotToReg, SlotToReg, #25
OperatorInstruction, RegToSlot, RegToSlot, SlotToReg, RegToSlot, #30 OperatorInstruction, RegToSlot, RegToSlot, SlotToReg, RegToSlot, #30
Branch, Branch, SlotToReg, SlotToReg, RegToSlot, #35 Branch, SlotToReg, SlotToReg, RegToSlot, SlotToReg, #35
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, #40 SlotToReg, FunctionReturn, SlotToReg, RegToSlot, Branch, #40
RegToSlot, Branch, SlotToReg, SlotToReg, RegToSlot, #45 SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #45
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer, #50 FunctionReturn, Transfer, SlotToReg, SlotToReg, Transfer, #50
SlotToReg, SlotToReg, Syscall, NilClass,] #55 Syscall, NilClass,] #55
assert_equal 1 , get_return assert_equal 1 , get_return
end end
def test_op def test_op
op = main_ticks(26) assert_operator 26 , :- , "message.receiver.data_1" , "message.arg1.data_1" , "op_-_"
assert_equal OperatorInstruction , op.class assert_equal 1 , @interpreter.get_register(@instruction.result)
assert_equal :- , op.operator assert_equal 6 , @interpreter.get_register(:"message.receiver.data_1")
assert_equal :r2 , op.left.symbol assert_equal 5 , @interpreter.get_register(:"message.arg1.data_1")
assert_equal :r3 , op.right.symbol
assert_equal 1 , @interpreter.get_register(:r2)
assert_equal 5 , @interpreter.get_register(:r3)
end end
def test_return def test_return
ret = main_ticks(49) ret = main_ticks(46)
assert_equal FunctionReturn , ret.class assert_equal FunctionReturn , ret.class
assert_equal :r3 , ret.register.symbol assert_equal :"message.return_address" , ret.register.symbol
assert_equal 36540 , @interpreter.get_register(ret.register) assert_equal 36572 , @interpreter.get_register(ret.register).value
end end
end end
end end

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@ -14,25 +14,21 @@ module Risc
#show_main_ticks # get output of what is #show_main_ticks # get output of what is
check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #5 check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #5
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, #10 RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, #10
FunctionCall, LoadConstant, SlotToReg, LoadConstant, OperatorInstruction, #15 FunctionCall, LoadConstant, LoadConstant, SlotToReg, OperatorInstruction, #15
IsNotZero, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #20 IsNotZero, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #20
LoadData, OperatorInstruction, RegToSlot, RegToSlot, SlotToReg, #25 LoadData, OperatorInstruction, RegToSlot, RegToSlot, SlotToReg, #25
RegToSlot, Branch, SlotToReg, SlotToReg, RegToSlot, #30 RegToSlot, Branch, SlotToReg, Branch, SlotToReg, #30
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, #35 RegToSlot, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, #35
RegToSlot, Branch, SlotToReg, SlotToReg, RegToSlot, #40 RegToSlot, Branch, SlotToReg, SlotToReg, RegToSlot, #40
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer, #45 SlotToReg, SlotToReg, FunctionReturn, Transfer, SlotToReg, #45
SlotToReg, SlotToReg, Syscall, NilClass,] #50 SlotToReg, Transfer, Syscall, NilClass,] #50
assert_equal 2 , get_return assert_equal 2 , get_return
end end
def test_op def test_op
op = main_ticks(22) assert_operator 22 , :>>, "message.receiver.data_1" , "integer_1" , "op_>>_"
assert_equal OperatorInstruction , op.class assert_equal 2 , @interpreter.get_register(:integer_1)
assert_equal :>> , op.operator assert_equal 9 , @interpreter.get_register(:"message.receiver.data_1")
assert_equal :r2 , op.left.symbol
assert_equal :r3 , op.right.symbol
assert_equal 2 , @interpreter.get_register(:r2)
assert_equal 2 , @interpreter.get_register(:r3)
end end
end end
end end

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@ -12,17 +12,17 @@ module Risc
def test_mult def test_mult
#show_main_ticks # get output of what is #show_main_ticks # get output of what is
check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #5 check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #5
RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, #10 RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, #10
SlotToReg, RegToSlot, SlotToReg, FunctionCall, LoadConstant, #15 SlotToReg, RegToSlot, SlotToReg, FunctionCall, LoadConstant, #15
SlotToReg, LoadConstant, OperatorInstruction, IsNotZero, SlotToReg, #20 LoadConstant, SlotToReg, OperatorInstruction, IsNotZero, SlotToReg, #20
RegToSlot, SlotToReg, SlotToReg, SlotToReg, SlotToReg, #25 RegToSlot, SlotToReg, SlotToReg, SlotToReg, SlotToReg, #25
OperatorInstruction, RegToSlot, RegToSlot, SlotToReg, RegToSlot, #30 OperatorInstruction, RegToSlot, RegToSlot, SlotToReg, RegToSlot, #30
Branch, Branch, SlotToReg, SlotToReg, RegToSlot, #35 Branch, SlotToReg, SlotToReg, RegToSlot, SlotToReg, #35
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, #40 SlotToReg, FunctionReturn, SlotToReg, RegToSlot, Branch, #40
RegToSlot, Branch, SlotToReg, SlotToReg, RegToSlot, #45 SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #45
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer, #50 FunctionReturn, Transfer, SlotToReg, SlotToReg, Transfer, #50
SlotToReg, SlotToReg, Syscall, NilClass,] #55 Syscall, NilClass,] #55
assert_equal 0 , get_return assert_equal 0 , get_return
end end
def test_zero def test_zero
@ -30,12 +30,9 @@ module Risc
assert @interpreter.flags[:zero] assert @interpreter.flags[:zero]
end end
def test_op def test_op
op = main_ticks(26) assert_operator 26 , :*, "message.receiver.data_1" , "message.arg1.data_1" , "op_*_"
assert_equal OperatorInstruction , op.class assert_equal 2147483648 , @interpreter.get_register(:"message.arg1.data_1")
assert_equal :r2 , op.left.symbol assert_equal 2147483648 , @interpreter.get_register(:"message.receiver.data_1")
assert_equal :r3 , op.right.symbol
assert_equal 0 , @interpreter.get_register(:r2)
assert_equal 2**31 , @interpreter.get_register(:r3)
end end
def test_overflow def test_overflow
main_ticks( 26 ) main_ticks( 26 )

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@ -25,22 +25,6 @@ module Risc
Syscall, NilClass,] #55 Syscall, NilClass,] #55
assert_equal 10 , get_return assert_equal 10 , get_return
end end
def test_base
assert_function_call 0 , :main
end
def test_load_receiver
assert_slot_to_reg( 22 , :message , 2 , "message.receiver")
end
def test_reduce_receiver
assert_slot_to_reg( 23 , "message.receiver" , 2 , "message.receiver.data_1" )
end
def test_slot_args #load args from message
assert_slot_to_reg( 24 , :message , 9 , "message.arg1")
end
def test_reduce_arg
assert_slot_to_reg( 25 , "message.arg1" , 2 , "message.arg1.data_1")
assert_equal 5 , @interpreter.get_register(:"message.arg1.data_1")
end
def test_op def test_op
assert_operator 26, :+ , "message.receiver.data_1" , "message.arg1.data_1" , "op_+_" assert_operator 26, :+ , "message.receiver.data_1" , "message.arg1.data_1" , "op_+_"
assert_equal 10 , @interpreter.get_register(@instruction.result.symbol) assert_equal 10 , @interpreter.get_register(@instruction.result.symbol)