moving many attributes into the attributes hash, but not nearly all

lib/arm/arm_machine.rb

@@ -1,5 +1,4 @@
 require "vm/machine"
-require_relative "instruction"
 require_relative "stack_instruction"
 require_relative "logic_instruction"
 require_relative "move_instruction"

lib/arm/call_instruction.rb

@@ -1,4 +1,3 @@
-require_relative "instruction"
 require_relative "nodes"
 
 module Arm
@@ -24,14 +23,12 @@ module Arm
 
     def initialize(attributes)
       super(attributes)
-      @update_status_flag = 0
+      @attributes[:update_status_flag] = 0
-      @condition_code = :al
+      @attributes[:condition_code] = :al
-      @opcode = attributes[:opcode]
-      @operand = 0
     end
     
     def assemble(io)
-      case @opcode
+      case @attributes[:opcode]
       when :b, :bl
         arg = @attributes[:left]
         #puts "BLAB #{arg.inspect}"
@@ -51,7 +48,7 @@ module Arm
         else
           raise "else not coded #{inspect}"
         end
-        io.write_uint8 OPCODES[opcode] | (COND_CODES[@condition_code] << 4)
+        io.write_uint8 OPCODES[opcode] | (COND_CODES[@attributes[:condition_code]] << 4)
       when :swi
         arg = @attributes[:left]
         if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
@@ -60,7 +57,7 @@ module Arm
         if (arg.is_a?(Arm::NumLiteral))
           packed = [arg.value].pack('L')[0,3]
           io << packed
-          io.write_uint8 0b1111 | (COND_CODES[@condition_code] << 4)
+          io.write_uint8 0b1111 | (COND_CODES[@attributes[:condition_code]] << 4)
         else
           raise "invalid operand argument expected literal not #{arg} #{inspect}"
         end

lib/arm/compare_instruction.rb

@@ -1,4 +1,3 @@
-require_relative "instruction"
 require_relative "logic_helper"
 
 module Arm
@@ -8,11 +7,11 @@ module Arm
 
     def initialize(attributes)
       super(attributes) 
-      @condition_code = :al
+      @attributes[:condition_code] = :al
-      @opcode = attributes[:opcode]
+      @attributes[:opcode] = attributes[:opcode]
       @operand = 0
       @i = 0      
-      @update_status_flag = 1
+      @attributes[:update_status_flag] = 1
       @rn = attributes[:left]
       @rd = :r0
     end

lib/arm/constants.rb

@@ -21,9 +21,9 @@ module Arm
       :bl => 0b1011,
       :bx => 0b00010010
     }
-    #return the bit patter that the cpu uses for the current instruction @opcode
+    #return the bit patter that the cpu uses for the current instruction @attributes[:opcode]
     def op_bit_code
-      OPCODES[@opcode] or throw "no code found for #{@opcode.inspect}"
+      OPCODES[@attributes[:opcode]] or throw "no code found for #{@attributes[:opcode].inspect}"
     end
 
     #codition codes can be applied to many instructions and thus save branches
@@ -39,9 +39,9 @@ module Arm
       :ge => 0b1010, :gt => 0b1100,
       :vs => 0b0110
     }
-    #return the bit pattern for the @condition_code variable, which signals the conditional code
+    #return the bit pattern for the @attributes[:condition_code] variable, which signals the conditional code
     def cond_bit_code
-      COND_CODES[@condition_code] or throw "no code found for #{@condition_code}"
+      COND_CODES[@attributes[:condition_code]] or throw "no code found for #{@attributes[:condition_code]}"
     end
     
     REGISTERS = { 'r0' => 0, 'r1' => 1, 'r2' => 2, 'r3' => 3, 'r4' => 4, 'r5' => 5,

lib/arm/instruction.rb

@@ -1,30 +0,0 @@
-require "vm/instruction"
-require_relative "constants"
-
-class Saved
-
-    def initializ(opcode , condition_code , update_status , args)
-      @update_status_flag = update_status
-      @condition_code = condition_code.to_sym
-      @opcode = opcode
-      @args = args
-      @operand = 0
-    end
-    
-    attr_reader :opcode, :args 
-    # Many arm instructions may be conditional, where the default condition is always (al)
-    # ArmMachine::COND_CODES names them, and this attribute reflects it
-    attr_reader :condition_code
-    attr_reader :operand
-
-    # Logic instructions may be executed with or without affecting the status register
-    # Only when an instruction affects the status is a subsequent compare instruction effective
-    # But to make the conditional execution (see cond) work for more than one instruction, one needs to
-    # be able to execute without changing the status 
-    attr_reader :update_status_flag
-    
-    # arm intrucioons are pretty sensible, and always 4 bytes (thumb not supported)
-    def length
-      4
-    end
-  end

lib/arm/logic_helper.rb

@@ -1,4 +1,3 @@
-require_relative "instruction"
 
 module Arm
   # Many arm instructions may be conditional, where the default condition is always (al)
@@ -84,7 +83,7 @@ module Arm
       raise inspect unless reg_code(@rd)
       val |= (reg_code(@rd) <<            12)     
       val |= (reg_code(@rn) <<            12+4)   
-      val |= (@update_status_flag << 12+4+4)#20 
+      val |= (@attributes[:update_status_flag] << 12+4+4)#20 
       val |= (op_bit_code <<        12+4+4  +1)
       val |= (@i <<                  12+4+4  +1+4) 
       val |= (instuction_class <<   12+4+4  +1+4+1) 

lib/arm/logic_instruction.rb

@@ -1,4 +1,3 @@
-require_relative "instruction"
 require_relative "logic_helper"
 
 module Arm
@@ -9,9 +8,9 @@ module Arm
 
     def initialize(attributes)
       super(attributes)
-      @update_status_flag = 0
+      @attributes[:update_status_flag] = 0
-      @condition_code = :al
+      @attributes[:condition_code] = :al
-      @opcode = attributes[:opcode]
+      @attributes[:opcode] = attributes[:opcode]
       @operand = 0
 
       @rn = nil

lib/arm/memory_instruction.rb

@@ -1,5 +1,4 @@
 require_relative "nodes"
-require_relative "instruction"
 
 module Arm
   # ADDRESSING MODE 2
@@ -9,9 +8,9 @@ module Arm
 
     def initialize(attributes)
       super(attributes)
-      @update_status_flag = 0
+      @attributes[:update_status_flag] = 0
-      @condition_code = :al
+      @attributes[:condition_code] = :al
-      @opcode = attributes[:opcode]
+      @attributes[:opcode] = attributes[:opcode]
       @operand = 0
 
       @i = 0 #I flag (third bit)
@@ -23,8 +22,7 @@ module Arm
       @rn = :r0 # register zero = zero bit pattern
       @rd = :r0 # register zero = zero bit pattern
     end
-    attr_accessor :i, :pre_post_index, :add_offset,
+#    attr_accessor :i, :pre_post_index, :add_offset, :byte_access, :w, :is_load, :rn, :rd
-                  :byte_access, :w, :is_load, :rn, :rd
 
     # arm intrucioons are pretty sensible, and always 4 bytes (thumb not supported)
     def length
@@ -82,14 +80,14 @@ module Arm
       @pre_post_index = 1
       instuction_class =  0b01 # OPC_MEMORY_ACCESS
       val = @operand.is_a?(Symbol) ? reg_code(@operand) : @operand 
-      val |= (reg_code(rd) <<        12 )  
+      val |= (reg_code(@rd) <<        12 )  
-      val |= (reg_code(rn) <<        12+4) #16  
+      val |= (reg_code(@rn) <<        12+4) #16  
-      val |= (is_load <<        12+4  +4)
+      val |= (@is_load <<        12+4  +4)
-      val |= (w <<              12+4  +4+1)
+      val |= (@w <<              12+4  +4+1)
-      val |= (byte_access <<    12+4  +4+1+1)
+      val |= (@byte_access <<    12+4  +4+1+1)
-      val |= (add_offset <<     12+4  +4+1+1+1)
+      val |= (@add_offset <<     12+4  +4+1+1+1)
-      val |= (pre_post_index << 12+4  +4+1+1+1+1)#24
+      val |= (@pre_post_index << 12+4  +4+1+1+1+1)#24
-      val |= (i <<              12+4  +4+1+1+1+1  +1) 
+      val |= (@i <<              12+4  +4+1+1+1+1  +1) 
       val |= (instuction_class<<12+4  +4+1+1+1+1  +1+1)  
       val |= (cond_bit_code <<  12+4  +4+1+1+1+1  +1+1+2)
       io.write_uint32 val

lib/arm/move_instruction.rb

@@ -1,4 +1,3 @@
-require_relative "instruction"
 require_relative "logic_helper"
 
 module Arm
@@ -9,9 +8,9 @@ module Arm
 
     def initialize(attributes) 
       super(attributes)
-      @update_status_flag = 0
+      @attributes[:update_status_flag] = 0
-      @condition_code = :al
+      @attributes[:condition_code] = :al
-      @opcode = attributes[:opcode]
+      @attributes[:opcode] = attributes[:opcode]
       @operand = 0
 
       @i = 0      

lib/arm/stack_instruction.rb

@@ -1,4 +1,5 @@
-require_relative "instruction"
+require "vm/instruction"
+require_relative "constants"
 
 module Arm
   # ADDRESSING MODE 4
@@ -12,40 +13,38 @@ module Arm
 
     def initialize(attributes)
       super(attributes) 
-      @update_status_flag = 0
+      @attributes[:update_status_flag] = 0
-      @condition_code = :al
+      @attributes[:condition_code] = :al
-      @opcode = attributes[:opcode]
+      @attributes[:opcode] = attributes[:opcode]
       @operand = 0
 
-      @update_status_flag= 0
+      @attributes[:update_status_flag]= 0
       @rn = :r0 # register zero = zero bit pattern
       # downward growing, decrement before memory access
       # official ARM style stack as used by gas
-      @write_base = 1
-      if (opcode == :push)
-        @pre_post_index = 1
-        @up_down = 0
-        @is_pop = 0
-      else  #pop
-        @pre_post_index = 0
-        @up_down = 1
-        @is_pop = 1
-      end
     end
-    attr_accessor :pre_post_index, :up_down,
-                  :update_status_flag, :write_base, :is_pop, :rn
                   
     def assemble(io)
       build
+      write_base = 1
+      if (opcode == :push)
+        pre_post_index = 1
+        up_down = 0
+        is_pop = 0
+      else  #pop
+        pre_post_index = 0
+        up_down = 1
+        is_pop = 1
+      end
       instuction_class = 0b10 # OPC_STACK
-      cond = @condition_code.is_a?(Symbol) ?  COND_CODES[@condition_code]   : @condition_code
+      cond = @attributes[:condition_code].is_a?(Symbol) ?  COND_CODES[@attributes[:condition_code]]   : @attributes[:condition_code]
       @rn = :sp # sp register
       #assemble of old
       val = @operand
       val |= (reg_code(@rn) <<             16)
       val |= (is_pop <<              16+4) #20
       val |= (write_base <<          16+4+ 1) 
-      val |= (update_status_flag <<  16+4+ 1+1) 
+      val |= (@attributes[:update_status_flag] <<  16+4+ 1+1) 
       val |= (up_down <<             16+4+ 1+1+1)
       val |= (pre_post_index <<      16+4+ 1+1+1+1)#24
       val |= (instuction_class <<    16+4+ 1+1+1+1 +2)