generalise the operator handling

ie passing them through
implementing more

lib/risc/boot.rb

@@ -181,7 +181,10 @@ module Risc
       end
 
       obj = space.get_class_by_name(:Integer)
-      [ :putint, :div4, :div10, :+ , :- , :*].each do |f|   #div4 is just a forward declaration
+      Risc.operators.each do |op|
+        obj.instance_type.add_method Builtin::Integer.operator_method(op)
+      end
+      [:putint, :div4, :div10].each do |f|   #div4 is just a forward declaration
         obj.instance_type.add_method Builtin::Integer.send(f , nil)
       end
     end

lib/risc/builtin/integer.rb

@@ -24,24 +24,15 @@ module Risc
           compiler.add_mom( Mom::ReturnSequence.new)
           return compiler.method
         end
-        def *( context )
-          operator_method( "mult" , :*)
-        end
-        def +( context )
-          operator_method( "plus" , :+)
-        end
-        def -( context )
-          operator_method( "minus" , :-)
-        end
-        def operator_method(op_name , op_sym )
+        def operator_method( op_sym )
           compiler = compiler_for(:Integer, op_sym ,{other: :Integer})
           builder = compiler.builder(true, compiler.method)
-          me , other = builder.self_and_int_arg(op_name + "load receiver and arg")
-          builder.reduce_int( op_name + " fix me", me )
-          builder.reduce_int( op_name + " fix arg", other )
-          builder.add_code Risc.op( op_name + " operator", op_sym , me , other)
-          builder.add_new_int(op_name + " new int", me , other)
-          builder.add_reg_to_slot( op_name + "save ret" , other , :message , :return_value)
+          me , other = builder.self_and_int_arg(op_sym.to_s + "load receiver and arg")
+          builder.reduce_int( op_sym.to_s + " fix me", me )
+          builder.reduce_int( op_sym.to_s + " fix arg", other )
+          builder.add_code Risc.op( op_sym.to_s + " operator", op_sym , me , other)
+          builder.add_new_int(op_sym.to_s + " new int", me , other)
+          builder.add_reg_to_slot( op_sym.to_s + "save ret" , other , :message , :return_value)
           compiler.add_mom( Mom::ReturnSequence.new)
           return compiler.method
         end

lib/risc/instructions/operator_instruction.rb

@@ -1,5 +1,8 @@
 module Risc
 
+  def self.operators
+    [:+, :-, :>>, :<<, :*, :&, :|]
+  end
   # Destructive operator instructions on the two registers given
   #
   # left = left OP right
@@ -11,7 +14,7 @@ module Risc
     def initialize( source , operator , left , right )
       super(source)
       @operator = operator
-      raise "unsuported operator :#{operator}:" unless [:+, :-, :>>, :<<, :*, :&, :|, :==].include?(operator)
+      raise "unsuported operator :#{operator}:" unless Risc.operators.include?(operator)
       @left = left
       @right = right
       raise "Not register #{left}" unless RiscValue.look_like_reg(left)

test/parfait/test_space.rb

@@ -34,7 +34,7 @@ class TestSpace < MiniTest::Test
 
   def test_integer
     int = Parfait.object_space.get_class_by_name :Integer
-    assert_equal 6, int.instance_type.method_names.get_length
+    assert_equal 10, int.instance_type.method_names.get_length
   end
 
   def test_classes_class

test/risc/builtin/test_simple_int.rb

@@ -29,6 +29,10 @@ module Risc
         run_all "4 * 4"
         assert_equal 16 , get_return.value
       end
+      def test_smaller
+        run_all "4 < 5"
+        assert_equal 16 , get_return.value
+      end
     end
   end
 end

test/risc/interpreter/test_dynamic_call.rb

@@ -18,12 +18,6 @@ module Risc
              Label, LoadConstant, SlotToReg, OperatorInstruction, IsZero,
              SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch,
              Label, LoadConstant, SlotToReg, OperatorInstruction, IsZero,
-             SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch,
-             Label, LoadConstant, SlotToReg, OperatorInstruction, IsZero,
-             SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch,
-             Label, LoadConstant, SlotToReg, OperatorInstruction, IsZero,
-             SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch,
-             Label, LoadConstant, SlotToReg, OperatorInstruction, IsZero,
              SlotToReg, OperatorInstruction, IsZero, Label, RegToSlot,
              Label, LoadConstant, SlotToReg, LoadConstant, SlotToReg,
              RegToSlot, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
@@ -53,16 +47,16 @@ module Risc
     end
 
     def test_dyn
-      cal = main_ticks(98)
+      cal = main_ticks(68)
       assert_equal DynamicJump ,  cal.class
     end
     #should end in exit, but doesn't, becasue resolve never returns
     def test_sys
-      sys = main_ticks(129)
+      sys = main_ticks(99)
       assert_equal Syscall ,  sys.class
     end
     def test_return
-      ret = main_ticks(127)
+      ret = main_ticks(97)
       assert_equal FunctionReturn ,  ret.class
       link = @interpreter.get_register( ret.register )
       assert_equal Label , link.class