fixing register order in some instructions

and their use
Arm is confusing as it has result as first arg
we use forward logic, i.e. from -> to
This commit is contained in:
Torsten Ruger
2015-06-27 20:09:21 +03:00
parent add79e5157
commit 97b4c469f8
6 changed files with 18 additions and 6 deletions

View File

@ -41,7 +41,7 @@ module Register
# load the frame/message from space by index
new_codes << GetSlot.new( space_tmp , 5 , frame_tmp )
# save the frame in real frame register
new_codes << RegisterTransfer.new( RegisterReference.frame_reg , frame_tmp )
new_codes << RegisterTransfer.new( frame_tmp , RegisterReference.frame_reg )
# get the next_frame
new_codes << GetSlot.new( frame_tmp , 2 , frame_tmp) # 2 index of next_frame
# save next frame into space