fix div10
by reducing the incoming integer to fixnum and then pushing the fixnum result into a new integer
This commit is contained in:
parent
5a861d4ed5
commit
8acfda457f
@ -29,13 +29,16 @@ module Risc
|
||||
|
||||
end
|
||||
def div10( context )
|
||||
s = "div_10"
|
||||
s = "div_10 "
|
||||
compiler = compiler_for(:Integer,:div10 ,{})
|
||||
me = compiler.add_known( :receiver )
|
||||
tmp = compiler.add_known( :receiver )
|
||||
q = compiler.add_known( :receiver )
|
||||
const = compiler.use_reg :Integer , 1
|
||||
compiler.add_load_data( s, 1 , const )
|
||||
compiler.reduce_int( s , me )
|
||||
compiler.reduce_int( s , tmp )
|
||||
compiler.reduce_int( s , q )
|
||||
const = compiler.use_reg :fixnum , 1
|
||||
compiler.add_load_data( s , 1 , const )
|
||||
# int tmp = self >> 1
|
||||
compiler.add_code Risc.op( s , :>> , tmp , const)
|
||||
# int q = self >> 2
|
||||
@ -80,10 +83,9 @@ module Risc
|
||||
# return q + tmp
|
||||
compiler.add_code Risc.op( s , :+ , q , tmp )
|
||||
|
||||
# compiler.add_new_int(me , other)
|
||||
# compiler.add_reg_to_slot( source + "5" , other , :message , :return_value)
|
||||
compiler.add_new_int(q , tmp)
|
||||
compiler.add_reg_to_slot( s , tmp , :message , :return_value)
|
||||
|
||||
compiler.add_reg_to_slot( s , q , :message , :return_value)
|
||||
compiler.add_mom( Mom::ReturnSequence.new)
|
||||
return compiler.method
|
||||
end
|
||||
|
@ -165,6 +165,9 @@ module Risc
|
||||
return int_arg
|
||||
end
|
||||
|
||||
|
||||
# assumed Integer in given register is replaced by the fixnum that it is holding
|
||||
def reduce_int( source , register )
|
||||
add_slot_to_reg( source + "int -> fix" , register , Parfait::Integer.integer_index , register)
|
||||
end
|
||||
end
|
||||
end
|
||||
|
@ -5,7 +5,7 @@ module Risc
|
||||
include Ticker
|
||||
|
||||
def setup
|
||||
@string_input = as_main("return 15.div10")
|
||||
@string_input = as_main("return 25.div10")
|
||||
super
|
||||
end
|
||||
|
||||
@ -22,19 +22,20 @@ module Risc
|
||||
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
|
||||
LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant,
|
||||
FunctionCall, Label, SlotToReg, SlotToReg, SlotToReg,
|
||||
LoadData, OperatorInstruction, LoadData, OperatorInstruction, OperatorInstruction,
|
||||
LoadData, Transfer, OperatorInstruction, OperatorInstruction, LoadData,
|
||||
Transfer, OperatorInstruction, OperatorInstruction, LoadData, Transfer,
|
||||
OperatorInstruction, OperatorInstruction, LoadData, OperatorInstruction, LoadData,
|
||||
Transfer, OperatorInstruction, OperatorInstruction, Transfer, LoadData,
|
||||
OperatorInstruction, LoadData, OperatorInstruction, OperatorInstruction, RegToSlot,
|
||||
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
|
||||
FunctionReturn, SlotToReg, SlotToReg, RegToSlot, SlotToReg,
|
||||
SlotToReg, SlotToReg, SlotToReg, LoadData, OperatorInstruction,
|
||||
LoadData, OperatorInstruction, OperatorInstruction, LoadData, Transfer,
|
||||
OperatorInstruction, OperatorInstruction, LoadData, Transfer, OperatorInstruction,
|
||||
OperatorInstruction, LoadData, Transfer, OperatorInstruction, OperatorInstruction,
|
||||
LoadData, OperatorInstruction, LoadData, Transfer, OperatorInstruction,
|
||||
OperatorInstruction, Transfer, LoadData, OperatorInstruction, LoadData,
|
||||
OperatorInstruction, OperatorInstruction, LoadConstant, SlotToReg, SlotToReg,
|
||||
RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
|
||||
RegToSlot, SlotToReg, SlotToReg, FunctionReturn, SlotToReg,
|
||||
SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
|
||||
SlotToReg, SlotToReg, FunctionReturn, Transfer, Syscall,
|
||||
NilClass]
|
||||
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
|
||||
FunctionReturn, Transfer, Syscall, NilClass]
|
||||
assert_equal Parfait::Integer , get_return.class
|
||||
#assert_equal 1 , get_return
|
||||
assert_equal 2 , get_return.value
|
||||
end
|
||||
|
||||
def test_call_main
|
||||
@ -42,22 +43,21 @@ module Risc
|
||||
assert_equal FunctionCall , call_ins.class
|
||||
assert :main , call_ins.method.name
|
||||
end
|
||||
def test_load_15
|
||||
def test_load_25
|
||||
load_ins = ticks 43
|
||||
assert_equal LoadConstant , load_ins.class
|
||||
assert_equal 15 , @interpreter.get_register(load_ins.register).value
|
||||
assert_equal 25 , @interpreter.get_register(load_ins.register).value
|
||||
end
|
||||
def test_sys
|
||||
sys = ticks(105)
|
||||
assert_equal Syscall , sys.class
|
||||
assert_equal :exit , sys.name
|
||||
end
|
||||
|
||||
def test_return
|
||||
ret = ticks(91)
|
||||
ret = ticks(99)
|
||||
assert_equal FunctionReturn , ret.class
|
||||
link = @interpreter.get_register( ret.register )
|
||||
assert_equal Label , link.class
|
||||
end
|
||||
def test_sys
|
||||
sys = ticks(113)
|
||||
assert_equal Syscall , sys.class
|
||||
assert_equal :exit , sys.name
|
||||
end
|
||||
end
|
||||
end
|
||||
|
Loading…
Reference in New Issue
Block a user