fix div10

by reducing the incoming integer to fixnum
and then pushing the fixnum result into a new integer
This commit is contained in:
Torsten Ruger 2018-04-01 14:50:13 +03:00
parent 5a861d4ed5
commit 8acfda457f
3 changed files with 33 additions and 28 deletions

View File

@ -29,13 +29,16 @@ module Risc
end end
def div10( context ) def div10( context )
s = "div_10" s = "div_10 "
compiler = compiler_for(:Integer,:div10 ,{}) compiler = compiler_for(:Integer,:div10 ,{})
me = compiler.add_known( :receiver ) me = compiler.add_known( :receiver )
tmp = compiler.add_known( :receiver ) tmp = compiler.add_known( :receiver )
q = compiler.add_known( :receiver ) q = compiler.add_known( :receiver )
const = compiler.use_reg :Integer , 1 compiler.reduce_int( s , me )
compiler.add_load_data( s, 1 , const ) compiler.reduce_int( s , tmp )
compiler.reduce_int( s , q )
const = compiler.use_reg :fixnum , 1
compiler.add_load_data( s , 1 , const )
# int tmp = self >> 1 # int tmp = self >> 1
compiler.add_code Risc.op( s , :>> , tmp , const) compiler.add_code Risc.op( s , :>> , tmp , const)
# int q = self >> 2 # int q = self >> 2
@ -80,10 +83,9 @@ module Risc
# return q + tmp # return q + tmp
compiler.add_code Risc.op( s , :+ , q , tmp ) compiler.add_code Risc.op( s , :+ , q , tmp )
# compiler.add_new_int(me , other) compiler.add_new_int(q , tmp)
# compiler.add_reg_to_slot( source + "5" , other , :message , :return_value) compiler.add_reg_to_slot( s , tmp , :message , :return_value)
compiler.add_reg_to_slot( s , q , :message , :return_value)
compiler.add_mom( Mom::ReturnSequence.new) compiler.add_mom( Mom::ReturnSequence.new)
return compiler.method return compiler.method
end end

View File

@ -165,6 +165,9 @@ module Risc
return int_arg return int_arg
end end
# assumed Integer in given register is replaced by the fixnum that it is holding
def reduce_int( source , register )
add_slot_to_reg( source + "int -> fix" , register , Parfait::Integer.integer_index , register)
end
end end
end end

View File

@ -5,7 +5,7 @@ module Risc
include Ticker include Ticker
def setup def setup
@string_input = as_main("return 15.div10") @string_input = as_main("return 25.div10")
super super
end end
@ -22,19 +22,20 @@ module Risc
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant, LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant,
FunctionCall, Label, SlotToReg, SlotToReg, SlotToReg, FunctionCall, Label, SlotToReg, SlotToReg, SlotToReg,
LoadData, OperatorInstruction, LoadData, OperatorInstruction, OperatorInstruction, SlotToReg, SlotToReg, SlotToReg, LoadData, OperatorInstruction,
LoadData, Transfer, OperatorInstruction, OperatorInstruction, LoadData, LoadData, OperatorInstruction, OperatorInstruction, LoadData, Transfer,
Transfer, OperatorInstruction, OperatorInstruction, LoadData, Transfer, OperatorInstruction, OperatorInstruction, LoadData, Transfer, OperatorInstruction,
OperatorInstruction, OperatorInstruction, LoadData, OperatorInstruction, LoadData, OperatorInstruction, LoadData, Transfer, OperatorInstruction, OperatorInstruction,
Transfer, OperatorInstruction, OperatorInstruction, Transfer, LoadData, LoadData, OperatorInstruction, LoadData, Transfer, OperatorInstruction,
OperatorInstruction, LoadData, OperatorInstruction, OperatorInstruction, RegToSlot, OperatorInstruction, Transfer, LoadData, OperatorInstruction, LoadData,
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, OperatorInstruction, OperatorInstruction, LoadConstant, SlotToReg, SlotToReg,
FunctionReturn, SlotToReg, SlotToReg, RegToSlot, SlotToReg, RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
RegToSlot, SlotToReg, SlotToReg, FunctionReturn, SlotToReg,
SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot, SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
SlotToReg, SlotToReg, FunctionReturn, Transfer, Syscall, SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
NilClass] FunctionReturn, Transfer, Syscall, NilClass]
assert_equal Parfait::Integer , get_return.class assert_equal Parfait::Integer , get_return.class
#assert_equal 1 , get_return assert_equal 2 , get_return.value
end end
def test_call_main def test_call_main
@ -42,22 +43,21 @@ module Risc
assert_equal FunctionCall , call_ins.class assert_equal FunctionCall , call_ins.class
assert :main , call_ins.method.name assert :main , call_ins.method.name
end end
def test_load_15 def test_load_25
load_ins = ticks 43 load_ins = ticks 43
assert_equal LoadConstant , load_ins.class assert_equal LoadConstant , load_ins.class
assert_equal 15 , @interpreter.get_register(load_ins.register).value assert_equal 25 , @interpreter.get_register(load_ins.register).value
end end
def test_sys
sys = ticks(105)
assert_equal Syscall , sys.class
assert_equal :exit , sys.name
end
def test_return def test_return
ret = ticks(91) ret = ticks(99)
assert_equal FunctionReturn , ret.class assert_equal FunctionReturn , ret.class
link = @interpreter.get_register( ret.register ) link = @interpreter.get_register( ret.register )
assert_equal Label , link.class assert_equal Label , link.class
end end
def test_sys
sys = ticks(113)
assert_equal Syscall , sys.class
assert_equal :exit , sys.name
end
end end
end end