fix div10
by reducing the incoming integer to fixnum and then pushing the fixnum result into a new integer
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5a861d4ed5
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@ -29,13 +29,16 @@ module Risc
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end
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end
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def div10( context )
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def div10( context )
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s = "div_10"
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s = "div_10 "
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compiler = compiler_for(:Integer,:div10 ,{})
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compiler = compiler_for(:Integer,:div10 ,{})
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me = compiler.add_known( :receiver )
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me = compiler.add_known( :receiver )
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tmp = compiler.add_known( :receiver )
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tmp = compiler.add_known( :receiver )
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q = compiler.add_known( :receiver )
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q = compiler.add_known( :receiver )
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const = compiler.use_reg :Integer , 1
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compiler.reduce_int( s , me )
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compiler.add_load_data( s, 1 , const )
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compiler.reduce_int( s , tmp )
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compiler.reduce_int( s , q )
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const = compiler.use_reg :fixnum , 1
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compiler.add_load_data( s , 1 , const )
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# int tmp = self >> 1
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# int tmp = self >> 1
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compiler.add_code Risc.op( s , :>> , tmp , const)
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compiler.add_code Risc.op( s , :>> , tmp , const)
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# int q = self >> 2
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# int q = self >> 2
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@ -80,10 +83,9 @@ module Risc
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# return q + tmp
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# return q + tmp
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compiler.add_code Risc.op( s , :+ , q , tmp )
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compiler.add_code Risc.op( s , :+ , q , tmp )
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# compiler.add_new_int(me , other)
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compiler.add_new_int(q , tmp)
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# compiler.add_reg_to_slot( source + "5" , other , :message , :return_value)
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compiler.add_reg_to_slot( s , tmp , :message , :return_value)
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compiler.add_reg_to_slot( s , q , :message , :return_value)
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compiler.add_mom( Mom::ReturnSequence.new)
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compiler.add_mom( Mom::ReturnSequence.new)
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return compiler.method
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return compiler.method
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end
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end
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@ -165,6 +165,9 @@ module Risc
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return int_arg
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return int_arg
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end
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end
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# assumed Integer in given register is replaced by the fixnum that it is holding
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def reduce_int( source , register )
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add_slot_to_reg( source + "int -> fix" , register , Parfait::Integer.integer_index , register)
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end
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end
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end
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end
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end
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@ -5,7 +5,7 @@ module Risc
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include Ticker
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include Ticker
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def setup
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def setup
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@string_input = as_main("return 15.div10")
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@string_input = as_main("return 25.div10")
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super
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super
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end
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end
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@ -22,19 +22,20 @@ module Risc
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SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
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SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
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LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant,
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LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant,
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FunctionCall, Label, SlotToReg, SlotToReg, SlotToReg,
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FunctionCall, Label, SlotToReg, SlotToReg, SlotToReg,
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LoadData, OperatorInstruction, LoadData, OperatorInstruction, OperatorInstruction,
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SlotToReg, SlotToReg, SlotToReg, LoadData, OperatorInstruction,
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LoadData, Transfer, OperatorInstruction, OperatorInstruction, LoadData,
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LoadData, OperatorInstruction, OperatorInstruction, LoadData, Transfer,
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Transfer, OperatorInstruction, OperatorInstruction, LoadData, Transfer,
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OperatorInstruction, OperatorInstruction, LoadData, Transfer, OperatorInstruction,
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OperatorInstruction, OperatorInstruction, LoadData, OperatorInstruction, LoadData,
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OperatorInstruction, LoadData, Transfer, OperatorInstruction, OperatorInstruction,
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Transfer, OperatorInstruction, OperatorInstruction, Transfer, LoadData,
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LoadData, OperatorInstruction, LoadData, Transfer, OperatorInstruction,
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OperatorInstruction, LoadData, OperatorInstruction, OperatorInstruction, RegToSlot,
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OperatorInstruction, Transfer, LoadData, OperatorInstruction, LoadData,
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SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
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OperatorInstruction, OperatorInstruction, LoadConstant, SlotToReg, SlotToReg,
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FunctionReturn, SlotToReg, SlotToReg, RegToSlot, SlotToReg,
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RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
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RegToSlot, SlotToReg, SlotToReg, FunctionReturn, SlotToReg,
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SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
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SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
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SlotToReg, SlotToReg, FunctionReturn, Transfer, Syscall,
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SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
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NilClass]
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FunctionReturn, Transfer, Syscall, NilClass]
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assert_equal Parfait::Integer , get_return.class
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assert_equal Parfait::Integer , get_return.class
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#assert_equal 1 , get_return
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assert_equal 2 , get_return.value
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end
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end
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def test_call_main
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def test_call_main
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@ -42,22 +43,21 @@ module Risc
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assert_equal FunctionCall , call_ins.class
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assert_equal FunctionCall , call_ins.class
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assert :main , call_ins.method.name
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assert :main , call_ins.method.name
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end
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end
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def test_load_15
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def test_load_25
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load_ins = ticks 43
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load_ins = ticks 43
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assert_equal LoadConstant , load_ins.class
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assert_equal LoadConstant , load_ins.class
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assert_equal 15 , @interpreter.get_register(load_ins.register).value
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assert_equal 25 , @interpreter.get_register(load_ins.register).value
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end
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end
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def test_sys
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sys = ticks(105)
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assert_equal Syscall , sys.class
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assert_equal :exit , sys.name
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end
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def test_return
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def test_return
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ret = ticks(91)
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ret = ticks(99)
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assert_equal FunctionReturn , ret.class
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assert_equal FunctionReturn , ret.class
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link = @interpreter.get_register( ret.register )
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link = @interpreter.get_register( ret.register )
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assert_equal Label , link.class
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assert_equal Label , link.class
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end
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end
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def test_sys
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sys = ticks(113)
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assert_equal Syscall , sys.class
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assert_equal :exit , sys.name
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end
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end
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end
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end
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end
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