fix div10
by reducing the incoming integer to fixnum and then pushing the fixnum result into a new integer
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@ -29,13 +29,16 @@ module Risc
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end
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def div10( context )
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s = "div_10"
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s = "div_10 "
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compiler = compiler_for(:Integer,:div10 ,{})
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me = compiler.add_known( :receiver )
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tmp = compiler.add_known( :receiver )
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q = compiler.add_known( :receiver )
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const = compiler.use_reg :Integer , 1
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compiler.add_load_data( s, 1 , const )
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compiler.reduce_int( s , me )
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compiler.reduce_int( s , tmp )
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compiler.reduce_int( s , q )
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const = compiler.use_reg :fixnum , 1
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compiler.add_load_data( s , 1 , const )
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# int tmp = self >> 1
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compiler.add_code Risc.op( s , :>> , tmp , const)
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# int q = self >> 2
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@ -80,10 +83,9 @@ module Risc
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# return q + tmp
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compiler.add_code Risc.op( s , :+ , q , tmp )
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# compiler.add_new_int(me , other)
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# compiler.add_reg_to_slot( source + "5" , other , :message , :return_value)
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compiler.add_new_int(q , tmp)
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compiler.add_reg_to_slot( s , tmp , :message , :return_value)
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compiler.add_reg_to_slot( s , q , :message , :return_value)
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compiler.add_mom( Mom::ReturnSequence.new)
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return compiler.method
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end
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@ -165,6 +165,9 @@ module Risc
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return int_arg
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end
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# assumed Integer in given register is replaced by the fixnum that it is holding
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def reduce_int( source , register )
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add_slot_to_reg( source + "int -> fix" , register , Parfait::Integer.integer_index , register)
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end
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end
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end
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