resetting registers to prevent overflow
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@ -12,6 +12,7 @@ module Phisol
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true_block = @method.source.new_block "if_true" # second, linked in after current, before merge
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false_block = @method.source.new_block "if_false" # directly next in order, ie if we don't jump we land here
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reset_regs
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is = process(condition)
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branch_class = Object.const_get "Register::Is#{branch_type.capitalize}"
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@method.source.add_code branch_class.new( condition , true_block )
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@ -19,10 +20,12 @@ module Phisol
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# compile the true block (as we think of it first, even it is second in sequential order)
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@method.source.current true_block
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reset_regs
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last = process_all(if_true).last
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# compile the false block
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@method.source.current false_block
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reset_regs
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last = process_all(if_false).last if if_false
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@method.source.add_code Register::Branch.new(statement, merge_block )
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