more work on instrucitons, mov this time
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@@ -4,7 +4,6 @@ module Arm
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class MoveInstruction < Vm::MoveInstruction
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include Arm::Constants
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include LogicHelper
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def initialize(first , attributes)
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super(first , attributes)
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@@ -13,13 +12,63 @@ module Arm
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@attributes[:opcode] = attributes[:opcode]
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@operand = 0
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@i = 0
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@rd = @first
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@immediate = 0
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@rn = :r0 # register zero = zero bit pattern
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end
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# arm intrucions are pretty sensible, and always 4 bytes (thumb not supported)
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def length
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4
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end
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def build
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do_build @attributes[:right]
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right = @attributes[:right]
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if right.is_a?(Vm::StringConstant)
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# do pc relative addressing with the difference to the instuction
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# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
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right = Vm::IntegerConstant.new( right.position - self.position - 8 )
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@rn = :pc
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end
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if( right.is_a? Fixnum ) #HACK to not have to change the code just now
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right = Vm::IntegerConstant.new( right )
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end
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if (right.is_a?(Vm::IntegerConstant))
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if (right.integer.fits_u8?)
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# no shifting needed
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@operand = right.integer
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@immediate = 1
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elsif (op_with_rot = calculate_u8_with_rr(right))
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@operand = op_with_rot
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@immediate = 1
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raise "hmm"
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else
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raise "cannot fit numeric literal argument in operand #{right.inspect}"
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end
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elsif (right.is_a?(Symbol) or right.is_a?(Vm::Integer))
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@operand = reg_code(right) #integer means the register the integer is in (otherwise constant)
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@immediate = 0 # ie not immediate is register
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else
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raise "invalid operand argument #{right.inspect} , #{inspect}"
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end
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shift_handling
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end
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def assemble(io)
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build
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instuction_class = 0b00 # OPC_DATA_PROCESSING
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val = shift(@operand , 0)
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val |= shift(reg_code(@first) , 12)
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val |= shift(reg_code(@rn) , 12+4)
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val |= shift(@attributes[:update_status_flag] , 12+4+4)#20
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val |= shift(op_bit_code , 12+4+4 +1)
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val |= shift(@immediate , 12+4+4 +1+4)
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val |= shift(instuction_class , 12+4+4 +1+4+1)
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val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
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io.write_uint32 val
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end
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def shift val , by
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raise "Not integer #{val}:#{val.class}" unless val.is_a? Fixnum
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val << by
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end
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end
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end
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end
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