From 7e2210f77248a5478f03ea82ec381b0cf3d6d845 Mon Sep 17 00:00:00 2001 From: Torsten Ruger Date: Fri, 16 May 2014 19:56:13 +0300 Subject: [PATCH] renaming update_status_flag to just update_status --- lib/arm/call_instruction.rb | 2 +- lib/arm/compare_instruction.rb | 2 +- lib/arm/logic_helper.rb | 4 ++-- lib/arm/logic_instruction.rb | 4 ++-- lib/arm/memory_instruction.rb | 2 +- lib/arm/move_instruction.rb | 4 ++-- lib/arm/stack_instruction.rb | 6 +++--- lib/vm/function.rb | 4 +++- test/arm/test_logic.rb | 4 ++++ test/test_small_program.rb | 2 +- 10 files changed, 20 insertions(+), 14 deletions(-) diff --git a/lib/arm/call_instruction.rb b/lib/arm/call_instruction.rb index 794c03b8..f6e072c2 100644 --- a/lib/arm/call_instruction.rb +++ b/lib/arm/call_instruction.rb @@ -22,7 +22,7 @@ module Arm def initialize(first, attributes) super(first , attributes) - @attributes[:update_status_flag] = 0 + @attributes[:update_status] = 0 @attributes[:condition_code] = :al if @attributes[:condition_code] == nil end diff --git a/lib/arm/compare_instruction.rb b/lib/arm/compare_instruction.rb index b6ae027e..d9cb6fb2 100644 --- a/lib/arm/compare_instruction.rb +++ b/lib/arm/compare_instruction.rb @@ -10,7 +10,7 @@ module Arm @attributes[:condition_code] = :al if @attributes[:condition_code] == nil @operand = 0 @i = 0 - @attributes[:update_status_flag] = 1 + @attributes[:update_status] = 1 @rn = first @rd = :r0 end diff --git a/lib/arm/logic_helper.rb b/lib/arm/logic_helper.rb index e575c44f..36d7aa3a 100644 --- a/lib/arm/logic_helper.rb +++ b/lib/arm/logic_helper.rb @@ -9,7 +9,7 @@ module Arm # Only when an instruction affects the status is a subsequent compare instruction effective # But to make the conditional execution (see cond) work for more than one instruction, one needs to # be able to execute without changing the status - #attr_reader :update_status_flag + #attr_reader :update_status module LogicHelper # ADDRESSING MODE 1 @@ -83,7 +83,7 @@ module Arm raise inspect unless reg_code(@rd) val |= shift(reg_code(@rd) , 12) val |= shift(reg_code(@rn) , 12+4) - val |= shift(@attributes[:update_status_flag] , 12+4+4)#20 + val |= shift(@attributes[:update_status] , 12+4+4)#20 val |= shift(op_bit_code , 12+4+4 +1) val |= shift(@i , 12+4+4 +1+4) val |= shift(instuction_class , 12+4+4 +1+4+1) diff --git a/lib/arm/logic_instruction.rb b/lib/arm/logic_instruction.rb index 4d3f6c06..57ce2aff 100644 --- a/lib/arm/logic_instruction.rb +++ b/lib/arm/logic_instruction.rb @@ -7,7 +7,7 @@ module Arm def initialize(first , attributes) super(first , attributes) - @attributes[:update_status_flag] = 0 if @attributes[:update_status_flag] == nil + @attributes[:update_status] = 0 if @attributes[:update_status] == nil @attributes[:condition_code] = :al if @attributes[:condition_code] == nil @operand = 0 @@ -61,7 +61,7 @@ module Arm val = shift(@operand , 0) val |= shift(reg_code(@first) , 12) val |= shift(reg_code(@left) , 12+4) - val |= shift(@attributes[:update_status_flag] , 12+4+4)#20 + val |= shift(@attributes[:update_status] , 12+4+4)#20 val |= shift(op_bit_code , 12+4+4 +1) val |= shift(@immediate , 12+4+4 +1+4) val |= shift(instuction_class , 12+4+4 +1+4+1) diff --git a/lib/arm/memory_instruction.rb b/lib/arm/memory_instruction.rb index 00ee66a0..494d74eb 100644 --- a/lib/arm/memory_instruction.rb +++ b/lib/arm/memory_instruction.rb @@ -8,7 +8,7 @@ module Arm def initialize(first , attributes) super(first , attributes) - @attributes[:update_status_flag] = 0 if @attributes[:update_status_flag] == nil + @attributes[:update_status] = 0 if @attributes[:update_status] == nil @attributes[:condition_code] = :al if @attributes[:condition_code] == nil @operand = 0 diff --git a/lib/arm/move_instruction.rb b/lib/arm/move_instruction.rb index 252c1579..20ce7c8e 100644 --- a/lib/arm/move_instruction.rb +++ b/lib/arm/move_instruction.rb @@ -7,7 +7,7 @@ module Arm def initialize(first , attributes) super(first , attributes) - @attributes[:update_status_flag] = 0 if @attributes[:update_status_flag] == nil + @attributes[:update_status] = 0 if @attributes[:update_status] == nil @attributes[:condition_code] = :al if @attributes[:condition_code] == nil @attributes[:opcode] = attributes[:opcode] @operand = 0 @@ -59,7 +59,7 @@ module Arm val = shift(@operand , 0) val |= shift(reg_code(@first) , 12) val |= shift(reg_code(@rn) , 12+4) - val |= shift(@attributes[:update_status_flag] , 12+4+4)#20 + val |= shift(@attributes[:update_status] , 12+4+4)#20 val |= shift(op_bit_code , 12+4+4 +1) val |= shift(@immediate , 12+4+4 +1+4) val |= shift(instuction_class , 12+4+4 +1+4+1) diff --git a/lib/arm/stack_instruction.rb b/lib/arm/stack_instruction.rb index b0601afc..6f0a7195 100644 --- a/lib/arm/stack_instruction.rb +++ b/lib/arm/stack_instruction.rb @@ -13,12 +13,12 @@ module Arm def initialize(first , attributes) super(first , attributes) - @attributes[:update_status_flag] = 0 if @attributes[:update_status_flag] == nil + @attributes[:update_status] = 0 if @attributes[:update_status] == nil @attributes[:condition_code] = :al if @attributes[:condition_code] == nil @attributes[:opcode] = attributes[:opcode] @operand = 0 - @attributes[:update_status_flag]= 0 + @attributes[:update_status]= 0 @rn = :r0 # register zero = zero bit pattern # downward growing, decrement before memory access # official ARM style stack as used by gas @@ -44,7 +44,7 @@ module Arm val |= (reg_code(@rn) << 16) val |= (is_pop << 16+4) #20 val |= (write_base << 16+4+ 1) - val |= (@attributes[:update_status_flag] << 16+4+ 1+1) + val |= (@attributes[:update_status] << 16+4+ 1+1) val |= (up_down << 16+4+ 1+1+1) val |= (pre_post_index << 16+4+ 1+1+1+1)#24 val |= (instuction_class << 16+4+ 1+1+1+1 +2) diff --git a/lib/vm/function.rb b/lib/vm/function.rb index 9ce5cc62..90e9b711 100644 --- a/lib/vm/function.rb +++ b/lib/vm/function.rb @@ -50,7 +50,9 @@ module Vm address += @body.length @exit.link_at(address,context) end - + def position + @entry.position + end def length @entry.length + @exit.length + @body.length end diff --git a/test/arm/test_logic.rb b/test/arm/test_logic.rb index b6d12763..b15c37b4 100644 --- a/test/arm/test_logic.rb +++ b/test/arm/test_logic.rb @@ -27,6 +27,10 @@ class TestLogic < MiniTest::Test code = @machine.sub :r2, left: :r0, right: 1 assert_code code, :sub , [0x01,0x20,0x40,0xe2] #e2 40 20 01 end + def test_subs + code = @machine.sub :r2, left: :r2, right: 1 , update_status: 1 + assert_code code, :sub , [0x01,0x20,0x52,0xe2] #e2 52 20 01 + end def test_orr code = @machine.orr :r2 , left: :r2 , right: :r3 assert_code code , :orr , [0x03,0x20,0x82,0xe1] #e1 82 20 03 diff --git a/test/test_small_program.rb b/test/test_small_program.rb index 638b0aad..c78a921d 100644 --- a/test/test_small_program.rb +++ b/test/test_small_program.rb @@ -18,7 +18,7 @@ class TestSmallProg < MiniTest::Test start = Vm::Block.new("start") add_code start start.instance_eval do - sub :r0, left: :r0, right: 1 , :update_status_flag => 1 #2 + sub :r0, left: :r0, right: 1 , :update_status => 1 #2 bne start ,{} #3 end end