at least its in shape to start debugging again (that must count as half full)

This commit is contained in:
Torsten Ruger
2014-05-05 22:21:11 +03:00
parent 69b04d930f
commit 7d20b5e2df
15 changed files with 154 additions and 160 deletions

View File

@@ -51,11 +51,13 @@ module Arm
'v6' => 9, 'rfp' => 9, 'sl' => 10, 'fp' => 11, 'ip' => 12, 'sp' => 13,
'lr' => 14, 'pc' => 15 }
def reg name
raise "no such register #{reg}" unless REGISTERS[name]
Asm::Register.new(name , REGISTERS[name])
code = reg_code name
raise "no such register #{name}" unless code
Arm::Register.new(name.to_sym , code )
end
def reg_code name
REGISTERS[name.to_s]
end
def calculate_u8_with_rr(arg)
parts = arg.value.to_s(2).rjust(32,'0').scan(/^(0*)(.+?)0*$/).flatten