at least its in shape to start debugging again (that must count as half full)
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@@ -51,11 +51,13 @@ module Arm
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'v6' => 9, 'rfp' => 9, 'sl' => 10, 'fp' => 11, 'ip' => 12, 'sp' => 13,
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'lr' => 14, 'pc' => 15 }
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def reg name
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raise "no such register #{reg}" unless REGISTERS[name]
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Asm::Register.new(name , REGISTERS[name])
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code = reg_code name
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raise "no such register #{name}" unless code
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Arm::Register.new(name.to_sym , code )
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end
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def reg_code name
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REGISTERS[name.to_s]
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end
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def calculate_u8_with_rr(arg)
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parts = arg.value.to_s(2).rjust(32,'0').scan(/^(0*)(.+?)0*$/).flatten
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