remove link exception class

This commit is contained in:
Torsten Ruger 2018-05-08 20:22:04 +03:00
parent cf06642768
commit 7ca7e92dda
6 changed files with 5 additions and 44 deletions

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@ -67,7 +67,7 @@ module Arm
end end
raise "Negatives not implemented #{right} " if right < 0 raise "Negatives not implemented #{right} " if right < 0
unless @extra unless @extra
puts "RELINK M at #{Risc::Position.get(self)}" #puts "RELINK M at #{Risc::Position.get(self)}"
@extra = 1 @extra = 1
insert ArmMachine.add( to , to , 0 ) #noop that we change below insert ArmMachine.add( to , to , 0 ) #noop that we change below
end end

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@ -12,7 +12,6 @@ module Risc
end end
# Go through and assemble all instructions. # Go through and assemble all instructions.
# Assembly may cause LinkException, which is caught by caller
def assemble( instruction ) def assemble( instruction )
@index = 1 @index = 1
while(instruction) while(instruction)
@ -27,19 +26,4 @@ module Risc
end end
end end
# A LinkException is raised when the arm code can't fit a constant into _one_
# instruction. This is kind of unavoidable with arm.
#
# Off course the problem could be fixed without the exception, but the exception
# means all subsequent Instructions, including labels/jump targets move.
# Thus changing jump instructions to those labels.
# So the whole method has to be reassembled and (at least) the instructions beyond
# repositioned. Ie a non-local problem, and so the Exception.
#
# Note: In the future i hope to have a more flexible system, possibly with position
# listeners and change events. Because positions chaning is normal, not exceptional.
#
class LinkException < Exception
end
end end

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@ -133,22 +133,6 @@ module Risc
# constant loads into one instruction. # constant loads into one instruction.
# #
def create_binary def create_binary
not_ok = 1
while(not_ok)
begin
return do_create_binary
rescue LinkException
not_ok += 1
log.debug "Relink #{not_ok}"
position_code
end
end
end
# have to retry until it works. Unfortunately (FIXME) jumps can go be both
# directions, and so already assembled codes get wrong by moving/ inserting
# instructions. And we end up assmebling all code again :-(
def do_create_binary
objects.each do |id , method| objects.each do |id , method|
next unless method.is_a? Parfait::TypedMethod next unless method.is_a? Parfait::TypedMethod
writer = BinaryWriter.new(method.binary) writer = BinaryWriter.new(method.binary)

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@ -72,7 +72,7 @@ module Risc
def write_any( obj ) def write_any( obj )
write_any_log( obj , "Write") write_any_log( obj , "Write")
if @stream.length != Position.get(obj).at if @stream.length != Position.get(obj).at
raise "Write #{obj.class}:0x#{obj.object_id.to_s(16)} at 0x#{stream_position.to_s(16)} not #{Position.get(obj)}" puts "Write #{obj.class}:0x#{obj.object_id.to_s(16)} at 0x#{stream_position.to_s(16)} not #{Position.get(obj)}"
end end
write_any_out(obj) write_any_out(obj)
write_any_log( obj , "Wrote") write_any_log( obj , "Wrote")

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@ -23,11 +23,8 @@ module Arm
def test_mov_big def test_mov_big
code = @machine.mov :r0, 0x222 # is not 8 bit and can't be rotated by the arm system in one instruction code = @machine.mov :r0, 0x222 # is not 8 bit and can't be rotated by the arm system in one instruction
Risc::Position.set(code,0,1) Risc::Position.set(code,0,1)
begin # mov 512(0x200) = e3 a0 0c 02 add 34(0x22) = e2 90 00 22 # mov 512(0x200) = e3 a0 0c 02 add 34(0x22) = e2 90 00 22
assert_code code , :mov , [ 0x02,0x0c,0xb0,0xe3] assert_code code , :mov , [ 0x02,0x0c,0xb0,0xe3]
rescue Risc::LinkException
retry
end
assert_code code.next , :add , [ 0x22,0x00,0x90,0xe2] assert_code code.next , :add , [ 0x22,0x00,0x90,0xe2]
end end
def test_mvn def test_mvn

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@ -34,11 +34,7 @@ module Risc
@machine.objects.each do |id , method| @machine.objects.each do |id , method|
next unless method.is_a? Parfait::TypedMethod next unless method.is_a? Parfait::TypedMethod
method.cpu_instructions.each do |ins| method.cpu_instructions.each do |ins|
begin
ins.assemble(DevNull.new) ins.assemble(DevNull.new)
rescue LinkException
ins.assemble(DevNull.new)
end
end end
end end
end end