moved registers to machine, changed return to 0 (from 7) and erased all integer references to registers

This commit is contained in:
Torsten Ruger
2014-06-10 13:29:01 +03:00
parent d7a60f2803
commit 7ca3207b3e
7 changed files with 45 additions and 29 deletions

View File

@ -9,6 +9,20 @@ require_relative "constants"
module Arm
class ArmMachine < Vm::RegisterMachine
# The constants are here for readablility, the code uses access functions below
RETURN_REG = :r0
TYPE_REG = :r1
RECEIVER_REG = :r2
def return_register
RETURN_REG
end
def type_register
TYPE_REG
end
def receiver_register
RECEIVER_REG
end
def integer_equals block , left , right
block << cmp( left , right )
@ -106,11 +120,11 @@ module Arm
end
def syscall block , num
sys_and_ret = Vm::Integer.new( Vm::Function::RETURN_REG )
#small todo, is this actually correct for all (that they return int)
sys_and_ret = Vm::Integer.new( Vm::RegisterMachine.instance.return_register )
block << mov( sys_and_ret , num )
block << swi( 0 )
#small todo, is this actually correct for all (that they return int)
block << mov( sys_and_ret , :r0 ) # syscall returns in r0, more to our return
block << mov( sys_and_ret , return_register ) # syscall returns in r0, more to our return
#todo should write type into r0 according to syscall
sys_and_ret
end

View File

@ -12,10 +12,10 @@ module Arm
@immediate = 0
@rn = :r0 # register zero = zero bit pattern
raise inspect if to.is_a?(Vm::Value) and
from.is_a?(Vm::Value) and
!@attributes[:shift_lsr] and
to.register_symbol == from.register_symbol
# NO-OP -> pass raise inspect if to.is_a?(Vm::Value) and
# from.is_a?(Vm::Value) and
# !@attributes[:shift_lsr] and
# to.register_symbol == from.register_symbol
raise "uups " if @to.register_symbol == :rr1
end