From 7a2160e9b4b2e7b4e5b2782750ddbe32c150c1da Mon Sep 17 00:00:00 2001 From: Torsten Ruger Date: Mon, 23 Apr 2018 19:39:16 +0300 Subject: [PATCH] fix comparison operator < implemented <= --- lib/risc/builtin/integer.rb | 12 ++-- test/risc/builtin/test_simple_int.rb | 8 +++ .../interpreter/conditional/test_larger.rb | 36 ++++++++++++ .../interpreter/conditional/test_smaller.rb | 36 ++++++++++++ .../interpreter/while/test_while_count.rb | 57 ++++++++++--------- 5 files changed, 117 insertions(+), 32 deletions(-) create mode 100644 test/risc/interpreter/conditional/test_larger.rb create mode 100644 test/risc/interpreter/conditional/test_smaller.rb diff --git a/lib/risc/builtin/integer.rb b/lib/risc/builtin/integer.rb index a8e40d4d..a86f48de 100644 --- a/lib/risc/builtin/integer.rb +++ b/lib/risc/builtin/integer.rb @@ -20,12 +20,12 @@ module Risc return compiler.method end def >( context ) - comparison( :> , Risc::IsMinus) + comparison( :> ) end def <( context ) - comparison( :< , Risc::IsPlus) + comparison( :< ) end - def comparison( operator , branch ) + def comparison( operator ) compiler = compiler_for(:Integer, operator ,{other: :Integer}) builder = compiler.builder(true, compiler.method) me , other = builder.self_and_int_arg("#{operator} load receiver and arg") @@ -33,8 +33,12 @@ module Risc merge_label = Risc.label(compiler.method , "merge_label_#{builder.object_id}") builder.reduce_int( "#{operator} fix me", me ) builder.reduce_int( "#{operator} fix arg", other ) + if(operator == :<) + me , other = other , me + end builder.add_code Risc.op( "#{operator} operator", :- , me , other) - builder.add_code branch.new( "#{operator} if", false_label) + builder.add_code IsMinus.new( "#{operator} if", false_label) + builder.add_code IsZero.new( "#{operator} if", false_label) builder.add_load_constant("#{operator} new int", Parfait.object_space.true_object , other) builder.add_code Risc::Branch.new("jump over false", merge_label) builder.add_code false_label diff --git a/test/risc/builtin/test_simple_int.rb b/test/risc/builtin/test_simple_int.rb index 19fa279b..d58f94e9 100644 --- a/test/risc/builtin/test_simple_int.rb +++ b/test/risc/builtin/test_simple_int.rb @@ -45,6 +45,10 @@ module Risc run_input "6 < 5" assert_equal Parfait::FalseClass , get_return.class end + def test_smaller_false_same + run_input "5 < 5" + assert_equal Parfait::FalseClass , get_return.class + end def test_larger_true run_input "5 > 4" assert_equal Parfait::TrueClass , get_return.class @@ -53,6 +57,10 @@ module Risc run_input "5 > 6" assert_equal Parfait::FalseClass , get_return.class end + def test_larger_false_same + run_input "5 > 5" + assert_equal Parfait::FalseClass , get_return.class + end end end end diff --git a/test/risc/interpreter/conditional/test_larger.rb b/test/risc/interpreter/conditional/test_larger.rb new file mode 100644 index 00000000..5ddd1729 --- /dev/null +++ b/test/risc/interpreter/conditional/test_larger.rb @@ -0,0 +1,36 @@ +require_relative "../helper" + +module Risc + class InterpreterLargerIf < MiniTest::Test + include Ticker + + def setup + @string_input = as_main 'if( 5 > 5 ); return "then";else;return "else";end' + super + end + + def test_if + #show_main_ticks # get output of what is in main + check_main_chain [Label, LoadConstant, LoadConstant, SlotToReg, RegToSlot, + RegToSlot, SlotToReg, SlotToReg, RegToSlot, SlotToReg, + SlotToReg, RegToSlot, SlotToReg, RegToSlot, SlotToReg, + RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, + SlotToReg, SlotToReg, RegToSlot, LoadConstant, SlotToReg, + RegToSlot, SlotToReg, LoadConstant, FunctionCall, Label, + SlotToReg, SlotToReg, SlotToReg, SlotToReg, SlotToReg, + OperatorInstruction, IsMinus, IsZero, Label, LoadConstant, + Label, RegToSlot, SlotToReg, SlotToReg, RegToSlot, + SlotToReg, SlotToReg, FunctionReturn, SlotToReg, SlotToReg, + RegToSlot, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, + IsZero, Label, LoadConstant, RegToSlot, SlotToReg, + SlotToReg, RegToSlot, SlotToReg, SlotToReg, FunctionReturn, + Transfer, Syscall, NilClass] + assert_equal Parfait::Word , get_return.class + assert_equal "else" , get_return.to_string + end + def test_exit + done = main_ticks(67) + assert_equal Syscall , done.class + end + end +end diff --git a/test/risc/interpreter/conditional/test_smaller.rb b/test/risc/interpreter/conditional/test_smaller.rb new file mode 100644 index 00000000..79d893d8 --- /dev/null +++ b/test/risc/interpreter/conditional/test_smaller.rb @@ -0,0 +1,36 @@ +require_relative "../helper" + +module Risc + class InterpreterSmallerIf < MiniTest::Test + include Ticker + + def setup + @string_input = as_main 'if( 5 < 5 ); return "then";else;return "else";end' + super + end + + def test_if + #show_main_ticks # get output of what is in main + check_main_chain [Label, LoadConstant, LoadConstant, SlotToReg, RegToSlot, + RegToSlot, SlotToReg, SlotToReg, RegToSlot, SlotToReg, + SlotToReg, RegToSlot, SlotToReg, RegToSlot, SlotToReg, + RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant, + SlotToReg, SlotToReg, RegToSlot, LoadConstant, SlotToReg, + RegToSlot, SlotToReg, LoadConstant, FunctionCall, Label, + SlotToReg, SlotToReg, SlotToReg, SlotToReg, SlotToReg, + OperatorInstruction, IsMinus, IsZero, Label, LoadConstant, + Label, RegToSlot, SlotToReg, SlotToReg, RegToSlot, + SlotToReg, SlotToReg, FunctionReturn, SlotToReg, SlotToReg, + RegToSlot, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, + IsZero, Label, LoadConstant, RegToSlot, SlotToReg, + SlotToReg, RegToSlot, SlotToReg, SlotToReg, FunctionReturn, + Transfer, Syscall, NilClass] + assert_equal Parfait::Word , get_return.class + assert_equal "else" , get_return.to_string + end + def test_exit + done = main_ticks(67) + assert_equal Syscall , done.class + end + end +end diff --git a/test/risc/interpreter/while/test_while_count.rb b/test/risc/interpreter/while/test_while_count.rb index af72fab2..e66083be 100644 --- a/test/risc/interpreter/while/test_while_count.rb +++ b/test/risc/interpreter/while/test_while_count.rb @@ -5,7 +5,7 @@ module Risc include Ticker def setup - @string_input = as_main 'a = 0; while( 0 > a); a = 1 + a;end;return a' + @string_input = as_main 'a = -1; while( 0 > a); a = 1 + a;end;return a' super end @@ -19,40 +19,41 @@ module Risc SlotToReg, SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant, FunctionCall, Label, SlotToReg, SlotToReg, SlotToReg, SlotToReg, SlotToReg, - OperatorInstruction, IsMinus, LoadConstant, Branch, Label, - RegToSlot, SlotToReg, SlotToReg, RegToSlot, SlotToReg, - SlotToReg, FunctionReturn, SlotToReg, SlotToReg, RegToSlot, - SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsZero, - LoadConstant, OperatorInstruction, IsZero, LoadConstant, LoadConstant, - SlotToReg, RegToSlot, RegToSlot, SlotToReg, SlotToReg, - RegToSlot, SlotToReg, SlotToReg, RegToSlot, SlotToReg, - RegToSlot, SlotToReg, RegToSlot, LoadConstant, SlotToReg, - RegToSlot, SlotToReg, SlotToReg, SlotToReg, SlotToReg, - RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, - LoadConstant, FunctionCall, Label, SlotToReg, SlotToReg, - SlotToReg, SlotToReg, SlotToReg, OperatorInstruction, LoadConstant, - SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot, - SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, - FunctionReturn, SlotToReg, SlotToReg, RegToSlot, Branch, - Label, LoadConstant, LoadConstant, SlotToReg, RegToSlot, - RegToSlot, SlotToReg, SlotToReg, RegToSlot, SlotToReg, - SlotToReg, RegToSlot, SlotToReg, RegToSlot, SlotToReg, - RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, - SlotToReg, SlotToReg, SlotToReg, RegToSlot, LoadConstant, - SlotToReg, RegToSlot, SlotToReg, LoadConstant, FunctionCall, - Label, SlotToReg, SlotToReg, SlotToReg, SlotToReg, - SlotToReg, OperatorInstruction, IsMinus, Label, LoadConstant, + OperatorInstruction, IsMinus, IsZero, LoadConstant, Branch, Label, RegToSlot, SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, - IsZero, Label, SlotToReg, SlotToReg, RegToSlot, + IsZero, LoadConstant, OperatorInstruction, IsZero, LoadConstant, + LoadConstant, SlotToReg, RegToSlot, RegToSlot, SlotToReg, + SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot, + SlotToReg, RegToSlot, SlotToReg, RegToSlot, LoadConstant, + SlotToReg, RegToSlot, SlotToReg, SlotToReg, SlotToReg, + SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, + SlotToReg, LoadConstant, FunctionCall, Label, SlotToReg, + SlotToReg, SlotToReg, SlotToReg, SlotToReg, OperatorInstruction, + LoadConstant, SlotToReg, SlotToReg, RegToSlot, RegToSlot, + RegToSlot, SlotToReg, SlotToReg, RegToSlot, SlotToReg, + SlotToReg, FunctionReturn, SlotToReg, SlotToReg, RegToSlot, + Branch, Label, LoadConstant, LoadConstant, SlotToReg, + RegToSlot, RegToSlot, SlotToReg, SlotToReg, RegToSlot, + SlotToReg, SlotToReg, RegToSlot, SlotToReg, RegToSlot, + SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, + SlotToReg, SlotToReg, SlotToReg, SlotToReg, RegToSlot, + LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant, + FunctionCall, Label, SlotToReg, SlotToReg, SlotToReg, + SlotToReg, SlotToReg, OperatorInstruction, IsMinus, IsZero, + Label, LoadConstant, Label, RegToSlot, SlotToReg, + SlotToReg, RegToSlot, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, - FunctionReturn, Transfer, Syscall, NilClass] + LoadConstant, OperatorInstruction, IsZero, Label, SlotToReg, + SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot, + SlotToReg, SlotToReg, FunctionReturn, Transfer, Syscall, + NilClass] assert_kind_of Parfait::Integer , get_return - assert_equal 1 , get_return.value + assert_equal 0 , get_return.value end def test_exit - done = main_ticks(183) + done = main_ticks(185) assert_equal Syscall , done.class end end