This commit is contained in:
Torsten Ruger
2018-03-14 17:39:49 +05:30
parent 6fe13fc2b7
commit 79b4b07ac4
3 changed files with 8 additions and 7 deletions

View File

@ -16,8 +16,8 @@ module Risc
# Produce a RegToSlot instruction.
# From and to are registers or symbols that can be transformed to a register by resolve_to_register
# index resolves with resolve_to_index.
def self.reg_to_slot source , from , to , index
from = resolve_to_register from
def self.reg_to_slot( source , from_reg , to , index )
from = resolve_to_register from_reg
index = resolve_to_index( to , index)
to = resolve_to_register to
RegToSlot.new( source, from , to , index)