fix slot_load for higher order left arguments

needed for getting args or frame of the target, for assigns
fixed ripples in tests
This commit is contained in:
Torsten Ruger 2018-03-19 15:47:40 +05:30
parent 483a7c4467
commit 7953ef3e39
7 changed files with 46 additions and 16 deletions

View File

@ -54,6 +54,14 @@ module Mom
when Symbol
left = Risc.message_reg
left_index = Risc.resolve_to_index(@left.known_object , @left.slots.first)
if @left.slots.length > 1
# swap the existing target (with a new reg) and update the index
new_left = compiler.use_reg( type )
const << Risc::SlotToReg.new( self , left ,left_index, new_left)
left = new_left
left_index = resolve_to_index(@left.slots[0] , @left.slots[1] ,compiler)
raise "more slots not implemented #{@left.slots}" if @left.slots.length > 2
end
when Parfait::CacheEntry
left = compiler.use_reg( :int )
left_index = Risc.resolve_to_index(:cache_entry , @left.slots.first)
@ -61,8 +69,7 @@ module Mom
raise "We have left #{@left.known_object}"
end
const << Risc.reg_to_slot(self, right , left, left_index)
compiler.release_reg(left) unless @left.known_object.is_a?(Symbol)
compiler.release_reg(right)
compiler.reset_regs
return const
end
@ -70,6 +77,8 @@ module Mom
case object
when :frame
type = compiler.method.frame
when :message , :next_message
type = Parfait.object_space.get_class_by_name(:Message).instance_type
when :arguments
type = compiler.method.arguments
when :receiver
@ -89,7 +98,7 @@ module Mom
# The first element is either a known type name (Capitalized symbol of the class name) ,
# or the symbol :message
# And subsequent symbols must be instance variables on the previous type.
# Examples: [:message , :receiver] or [:Space : :next_message]
# Examples: [:message , :receiver] or [:Space , :next_message]
def initialize( object , slots)
@known_object , @slots = object , slots
slot = [slot] unless slot.is_a?(Array)

View File

@ -7,7 +7,7 @@ module Risc
def setup
super
@input = "arg = 5"
@expect = [LoadConstant, RegToSlot]
@expect = [LoadConstant, SlotToReg, RegToSlot]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg
@ -20,7 +20,12 @@ module Risc
def test_slot_move
produced = produce_body
assert_equal produced.next.register , produced.register
assert_equal produced.next(2).register , produced.register
end
def test_load_args_from_message
produced = produce_body
assert_equal :r0 , produced.next.array.symbol , produced.next.to_rxf
assert_equal 9 , produced.next.index , produced.next.to_rxf
end
end

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@ -7,7 +7,7 @@ module Risc
def setup
super
@input = "@ivar = 5"
@expect = [LoadConstant, RegToSlot]
@expect = [LoadConstant, SlotToReg, RegToSlot]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg
@ -20,7 +20,13 @@ module Risc
def test_slot_move
produced = produce_body
assert_equal produced.next.register , produced.register
assert_equal produced.next.next.register , produced.register
end
def test_load_self_from_message
produced = produce_body
assert_equal :r0 , produced.next.array.symbol , produced.next.to_rxf
assert_equal 3 , produced.next.index , produced.next.to_rxf
end
end

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@ -7,7 +7,7 @@ module Risc
def setup
super
@input = "local = arg"
@expect = [SlotToReg, SlotToReg, RegToSlot]
@expect = [SlotToReg, SlotToReg, SlotToReg, RegToSlot]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg
@ -15,8 +15,17 @@ module Risc
def test_slot_move
produced = produce_body
assert_equal produced.next.next.register , produced.register
assert_equal produced.next(3).register , produced.register
end
def test_load_args_from_message
produced = produce_body
assert_equal :r0 , produced.array.symbol , produced.next.to_rxf
assert_equal 9 , produced.index , produced.next.to_rxf
end
def test_load_frame_from_message
produced = produce_body
assert_equal :r0 , produced.next(2).array.symbol , produced.next.to_rxf
assert_equal 2 , produced.next.index , produced.next.to_rxf
end
end
end

View File

@ -7,7 +7,7 @@ module Risc
def setup
super
@input = "r = 5"
@expect = [LoadConstant, RegToSlot]
@expect = [LoadConstant,SlotToReg, RegToSlot]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg
@ -20,7 +20,7 @@ module Risc
def test_slot_move
produced = produce_body
assert_equal produced.next.register , produced.register
assert_equal produced.next(2).register , produced.register
end
end

View File

@ -7,7 +7,8 @@ module Risc
def setup
super
@input = "@ivar = 5 ; r = @ivar"
@expect = [LoadConstant, RegToSlot, SlotToReg, SlotToReg, RegToSlot]
@expect = [LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg, SlotToReg ,
RegToSlot]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg
@ -20,7 +21,7 @@ module Risc
def test_slot_move
produced = produce_body
assert_equal produced.next.register , produced.register
assert_equal produced.next(2).register , produced.register
end
end

View File

@ -7,8 +7,8 @@ module Risc
def setup
super
@input = "r = 5.mod4"
@expect = [Label, LoadConstant, RegToSlot, Label, Label, SlotToReg ,
RegToSlot]
@expect = [Label, LoadConstant, SlotToReg, RegToSlot, Label, Label ,
SlotToReg, SlotToReg, RegToSlot]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg