ruby-x/rubyx
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

change operators to symbols

Browse Source
This commit is contained in:
Torsten Ruger 2018-03-24 17:53:27 +02:00
parent 3ceb2c2f69
commit 793fa313a5
3 changed files with 37 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
lib/risc/builtin/integer.rb
View File

@ -25,48 +25,48 @@ module Risc
const = compiler.use_reg :Integer , 1
compiler.add_load_constant( s, 1 , const )
# int tmp = self >> 1
compiler.add_code Risc.op( s , ">>" , tmp , const)
compiler.add_code Risc.op( s , :>> , tmp , const)
# int q = self >> 2
compiler.add_load_constant( s , 2 , const)
compiler.add_code Risc.op( s , ">>" , q , const)
compiler.add_code Risc.op( s , :>> , q , const)
# q = q + tmp
compiler.add_code Risc.op( s , "+" , q , tmp )
compiler.add_code Risc.op( s , :+ , q , tmp )
# tmp = q >> 4
compiler.add_load_constant( s , 4 , const)
compiler.add_transfer( s, q , tmp)
compiler.add_code Risc.op( s , ">>" , tmp , const)
compiler.add_code Risc.op( s , :>> , tmp , const)
# q = q + tmp
compiler.add_code Risc.op( s , "+" , q , tmp )
compiler.add_code Risc.op( s , :+ , q , tmp )
# tmp = q >> 8
compiler.add_load_constant( s , 8 , const)
compiler.add_transfer( s, q , tmp)
compiler.add_code Risc.op( s , ">>" , tmp , const)
compiler.add_code Risc.op( s , :>> , tmp , const)
# q = q + tmp
compiler.add_code Risc.op( s , "+" , q , tmp )
compiler.add_code Risc.op( s , :+ , q , tmp )
# tmp = q >> 16
compiler.add_load_constant( s , 16 , const)
compiler.add_transfer( s, q , tmp)
compiler.add_code Risc.op( s , ">>" , tmp , const)
compiler.add_code Risc.op( s , :>> , tmp , const)
# q = q + tmp
compiler.add_code Risc.op( s , "+" , q , tmp )
compiler.add_code Risc.op( s , :+ , q , tmp )
# q = q >> 3
compiler.add_load_constant( s , 3 , const)
compiler.add_code Risc.op( s , ">>" , q , const)
compiler.add_code Risc.op( s , :>> , q , const)
# tmp = q * 10
compiler.add_load_constant( s , 10 , const)
compiler.add_transfer( s, q , tmp)
compiler.add_code Risc.op( s , "*" , tmp , const)
compiler.add_code Risc.op( s , :* , tmp , const)
# tmp = self - tmp
compiler.add_code Risc.op( s , "-" , me , tmp )
compiler.add_code Risc.op( s , :- , me , tmp )
compiler.add_transfer( s , me , tmp)
# tmp = tmp + 6
compiler.add_load_constant( s , 6 , const)
compiler.add_code Risc.op( s , "+" , tmp , const )
compiler.add_code Risc.op( s , :+ , tmp , const )
# tmp = tmp >> 4
compiler.add_load_constant( s , 4 , const)
compiler.add_code Risc.op( s , ">>" , tmp , const )
compiler.add_code Risc.op( s , :>> , tmp , const )
# return q + tmp
compiler.add_code Risc.op( s , "+" , q , tmp )
compiler.add_code Risc.op( s , :+ , q , tmp )
compiler.add_reg_to_slot( s , q , :message , :return_value)
compiler.add_mom( Mom::ReturnSequence.new)
return compiler.method

14
lib/risc/instructions/operator_instruction.rb
View File

@ -1,9 +1,17 @@
module Risc
# Destructive operator instructions on the two registers given
#
# left = left OP right
#
# With OP being the normal logical and mathematical operations provided by
# cpus. Ie "+" , "-", ">>", "<<", "*", "&", "|"
#
class OperatorInstruction < Instruction
def initialize source , operator , left , right
def initialize( source , operator , left , right )
super(source)
@operator = operator
raise "unsuported operator :#{operator}:" unless [:+, :-, :>>, :<<, :*, :&, :|, :==].include?(operator)
@left = left
@right = right
end
@ -14,8 +22,8 @@ module Risc
end
end
def self.op source , operator , left , right
OperatorInstruction.new source , operator , left , right
def self.op( source , operator , left , right )
OperatorInstruction.new( source , operator , left , right )
end
end

22
lib/risc/interpreter.rb
View File

@ -109,7 +109,7 @@ module Risc
def execute_IsZero
@flags[:zero] ? execute_Branch : true
end
def execute_IsNotzero
def execute_IsNotZero
@flags[:zero] ? true : execute_Branch
end
def execute_IsPlus
@ -255,23 +255,23 @@ module Risc
end
def handle_operator(left, right)
case @instruction.operator.to_s
when "+"
left = left.object_id unless left.is_a?(Integer)
right = right.object_id unless right.is_a?(Integer)
case @instruction.operator
when :+
return left + right
when "-"
when :-
return left - right
when ">>"
when :>>
return left / (2**right)
when "<<"
when :<<
return left * (2**right)
when "*"
when :*
return left * right
when "&"
when :&
return left & right
when "|"
when :|
return left | right
when "=="
return (left == right) ? 1 : 0
else
raise "unimplemented '#{@instruction.operator}' #{@instruction}"
end