change operators to symbols
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@ -25,48 +25,48 @@ module Risc
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const = compiler.use_reg :Integer , 1
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const = compiler.use_reg :Integer , 1
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compiler.add_load_constant( s, 1 , const )
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compiler.add_load_constant( s, 1 , const )
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# int tmp = self >> 1
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# int tmp = self >> 1
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compiler.add_code Risc.op( s , ">>" , tmp , const)
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compiler.add_code Risc.op( s , :>> , tmp , const)
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# int q = self >> 2
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# int q = self >> 2
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compiler.add_load_constant( s , 2 , const)
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compiler.add_load_constant( s , 2 , const)
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compiler.add_code Risc.op( s , ">>" , q , const)
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compiler.add_code Risc.op( s , :>> , q , const)
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# q = q + tmp
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# q = q + tmp
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compiler.add_code Risc.op( s , "+" , q , tmp )
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compiler.add_code Risc.op( s , :+ , q , tmp )
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# tmp = q >> 4
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# tmp = q >> 4
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compiler.add_load_constant( s , 4 , const)
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compiler.add_load_constant( s , 4 , const)
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compiler.add_transfer( s, q , tmp)
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compiler.add_transfer( s, q , tmp)
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compiler.add_code Risc.op( s , ">>" , tmp , const)
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compiler.add_code Risc.op( s , :>> , tmp , const)
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# q = q + tmp
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# q = q + tmp
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compiler.add_code Risc.op( s , "+" , q , tmp )
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compiler.add_code Risc.op( s , :+ , q , tmp )
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# tmp = q >> 8
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# tmp = q >> 8
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compiler.add_load_constant( s , 8 , const)
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compiler.add_load_constant( s , 8 , const)
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compiler.add_transfer( s, q , tmp)
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compiler.add_transfer( s, q , tmp)
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compiler.add_code Risc.op( s , ">>" , tmp , const)
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compiler.add_code Risc.op( s , :>> , tmp , const)
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# q = q + tmp
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# q = q + tmp
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compiler.add_code Risc.op( s , "+" , q , tmp )
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compiler.add_code Risc.op( s , :+ , q , tmp )
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# tmp = q >> 16
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# tmp = q >> 16
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compiler.add_load_constant( s , 16 , const)
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compiler.add_load_constant( s , 16 , const)
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compiler.add_transfer( s, q , tmp)
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compiler.add_transfer( s, q , tmp)
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compiler.add_code Risc.op( s , ">>" , tmp , const)
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compiler.add_code Risc.op( s , :>> , tmp , const)
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# q = q + tmp
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# q = q + tmp
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compiler.add_code Risc.op( s , "+" , q , tmp )
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compiler.add_code Risc.op( s , :+ , q , tmp )
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# q = q >> 3
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# q = q >> 3
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compiler.add_load_constant( s , 3 , const)
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compiler.add_load_constant( s , 3 , const)
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compiler.add_code Risc.op( s , ">>" , q , const)
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compiler.add_code Risc.op( s , :>> , q , const)
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# tmp = q * 10
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# tmp = q * 10
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compiler.add_load_constant( s , 10 , const)
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compiler.add_load_constant( s , 10 , const)
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compiler.add_transfer( s, q , tmp)
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compiler.add_transfer( s, q , tmp)
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compiler.add_code Risc.op( s , "*" , tmp , const)
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compiler.add_code Risc.op( s , :* , tmp , const)
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# tmp = self - tmp
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# tmp = self - tmp
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compiler.add_code Risc.op( s , "-" , me , tmp )
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compiler.add_code Risc.op( s , :- , me , tmp )
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compiler.add_transfer( s , me , tmp)
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compiler.add_transfer( s , me , tmp)
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# tmp = tmp + 6
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# tmp = tmp + 6
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compiler.add_load_constant( s , 6 , const)
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compiler.add_load_constant( s , 6 , const)
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compiler.add_code Risc.op( s , "+" , tmp , const )
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compiler.add_code Risc.op( s , :+ , tmp , const )
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# tmp = tmp >> 4
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# tmp = tmp >> 4
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compiler.add_load_constant( s , 4 , const)
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compiler.add_load_constant( s , 4 , const)
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compiler.add_code Risc.op( s , ">>" , tmp , const )
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compiler.add_code Risc.op( s , :>> , tmp , const )
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# return q + tmp
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# return q + tmp
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compiler.add_code Risc.op( s , "+" , q , tmp )
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compiler.add_code Risc.op( s , :+ , q , tmp )
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compiler.add_reg_to_slot( s , q , :message , :return_value)
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compiler.add_reg_to_slot( s , q , :message , :return_value)
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compiler.add_mom( Mom::ReturnSequence.new)
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compiler.add_mom( Mom::ReturnSequence.new)
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return compiler.method
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return compiler.method
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@ -1,9 +1,17 @@
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module Risc
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module Risc
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# Destructive operator instructions on the two registers given
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#
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# left = left OP right
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#
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# With OP being the normal logical and mathematical operations provided by
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# cpus. Ie "+" , "-", ">>", "<<", "*", "&", "|"
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#
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class OperatorInstruction < Instruction
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class OperatorInstruction < Instruction
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def initialize source , operator , left , right
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def initialize( source , operator , left , right )
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super(source)
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super(source)
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@operator = operator
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@operator = operator
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raise "unsuported operator :#{operator}:" unless [:+, :-, :>>, :<<, :*, :&, :|, :==].include?(operator)
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@left = left
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@left = left
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@right = right
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@right = right
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end
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end
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@ -14,8 +22,8 @@ module Risc
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end
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end
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end
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end
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def self.op source , operator , left , right
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def self.op( source , operator , left , right )
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OperatorInstruction.new source , operator , left , right
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OperatorInstruction.new( source , operator , left , right )
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end
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end
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end
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end
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@ -109,7 +109,7 @@ module Risc
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def execute_IsZero
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def execute_IsZero
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@flags[:zero] ? execute_Branch : true
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@flags[:zero] ? execute_Branch : true
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end
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end
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def execute_IsNotzero
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def execute_IsNotZero
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@flags[:zero] ? true : execute_Branch
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@flags[:zero] ? true : execute_Branch
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end
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end
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def execute_IsPlus
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def execute_IsPlus
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@ -255,23 +255,23 @@ module Risc
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end
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end
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def handle_operator(left, right)
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def handle_operator(left, right)
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case @instruction.operator.to_s
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left = left.object_id unless left.is_a?(Integer)
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when "+"
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right = right.object_id unless right.is_a?(Integer)
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case @instruction.operator
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when :+
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return left + right
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return left + right
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when "-"
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when :-
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return left - right
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return left - right
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when ">>"
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when :>>
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return left / (2**right)
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return left / (2**right)
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when "<<"
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when :<<
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return left * (2**right)
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return left * (2**right)
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when "*"
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when :*
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return left * right
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return left * right
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when "&"
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when :&
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return left & right
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return left & right
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when "|"
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when :|
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return left | right
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return left | right
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when "=="
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return (left == right) ? 1 : 0
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else
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else
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raise "unimplemented '#{@instruction.operator}' #{@instruction}"
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raise "unimplemented '#{@instruction.operator}' #{@instruction}"
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end
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end
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